1 /*
2 * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8
9 #include <arch_helpers.h>
10 #include <common/debug.h>
11 #include <drivers/delay_timer.h>
12 #include <drivers/st/stm32mp1_usb.h>
13 #include <lib/mmio.h>
14
15 #include <platform_def.h>
16
17 #define USB_OTG_MODE_DEVICE 0U
18 #define USB_OTG_MODE_HOST 1U
19 #define USB_OTG_MODE_DRD 2U
20
21 #define EP_TYPE_CTRL 0U
22 #define EP_TYPE_ISOC 1U
23 #define EP_TYPE_BULK 2U
24 #define EP_TYPE_INTR 3U
25
26 #define USBD_FIFO_FLUSH_TIMEOUT_US 1000U
27 #define EP0_FIFO_SIZE 64U
28
29 /* OTG registers offsets */
30 #define OTG_GOTGINT 0x004U
31 #define OTG_GAHBCFG 0x008U
32 #define OTG_GUSBCFG 0x00CU
33 #define OTG_GRSTCTL 0x010U
34 #define OTG_GINTSTS 0x014U
35 #define OTG_GINTMSK 0x018U
36 #define OTG_GRXSTSP 0x020U
37 #define OTG_GLPMCFG 0x054U
38 #define OTG_DCFG 0x800U
39 #define OTG_DCTL 0x804U
40 #define OTG_DSTS 0x808U
41 #define OTG_DIEPMSK 0x810U
42 #define OTG_DOEPMSK 0x814U
43 #define OTG_DAINT 0x818U
44 #define OTG_DAINTMSK 0x81CU
45 #define OTG_DIEPEMPMSK 0x834U
46
47 /* Definitions for OTG_DIEPx registers */
48 #define OTG_DIEP_BASE 0x900U
49 #define OTG_DIEP_SIZE 0x20U
50 #define OTG_DIEPCTL 0x00U
51 #define OTG_DIEPINT 0x08U
52 #define OTG_DIEPTSIZ 0x10U
53 #define OTG_DIEPDMA 0x14U
54 #define OTG_DTXFSTS 0x18U
55 #define OTG_DIEP_MAX_NB 9U
56
57 /* Definitions for OTG_DOEPx registers */
58 #define OTG_DOEP_BASE 0xB00U
59 #define OTG_DOEP_SIZE 0x20U
60 #define OTG_DOEPCTL 0x00U
61 #define OTG_DOEPINT 0x08U
62 #define OTG_DOEPTSIZ 0x10U
63 #define OTG_DOEPDMA 0x14U
64 #define OTG_D0EP_MAX_NB 9U
65
66 /* Definitions for OTG_DAINT registers */
67 #define OTG_DAINT_OUT_MASK GENMASK(31, 16)
68 #define OTG_DAINT_OUT_SHIFT 16U
69 #define OTG_DAINT_IN_MASK GENMASK(15, 0)
70 #define OTG_DAINT_IN_SHIFT 0U
71
72 #define OTG_DAINT_EP0_IN BIT(16)
73 #define OTG_DAINT_EP0_OUT BIT(0)
74
75 /* Definitions for FIFOs */
76 #define OTG_FIFO_BASE 0x1000U
77 #define OTG_FIFO_SIZE 0x1000U
78
79 /* Bit definitions for OTG_GOTGINT register */
80 #define OTG_GOTGINT_SEDET BIT(2)
81
82 /* Bit definitions for OTG_GAHBCFG register */
83 #define OTG_GAHBCFG_GINT BIT(0)
84
85 /* Bit definitions for OTG_GUSBCFG register */
86 #define OTG_GUSBCFG_TRDT GENMASK(13, 10)
87 #define OTG_GUSBCFG_TRDT_SHIFT 10U
88
89 #define USBD_HS_TRDT_VALUE 9U
90
91 /* Bit definitions for OTG_GRSTCTL register */
92 #define OTG_GRSTCTL_RXFFLSH BIT(4)
93 #define OTG_GRSTCTL_TXFFLSH BIT(5)
94 #define OTG_GRSTCTL_TXFNUM_SHIFT 6U
95
96 /* Bit definitions for OTG_GINTSTS register */
97 #define OTG_GINTSTS_CMOD BIT(0)
98 #define OTG_GINTSTS_MMIS BIT(1)
99 #define OTG_GINTSTS_OTGINT BIT(2)
100 #define OTG_GINTSTS_SOF BIT(3)
101 #define OTG_GINTSTS_RXFLVL BIT(4)
102 #define OTG_GINTSTS_USBSUSP BIT(11)
103 #define OTG_GINTSTS_USBRST BIT(12)
104 #define OTG_GINTSTS_ENUMDNE BIT(13)
105 #define OTG_GINTSTS_IEPINT BIT(18)
106 #define OTG_GINTSTS_OEPINT BIT(19)
107 #define OTG_GINTSTS_IISOIXFR BIT(20)
108 #define OTG_GINTSTS_IPXFR_INCOMPISOOUT BIT(21)
109 #define OTG_GINTSTS_LPMINT BIT(27)
110 #define OTG_GINTSTS_SRQINT BIT(30)
111 #define OTG_GINTSTS_WKUPINT BIT(31)
112
113 /* Bit definitions for OTG_GRXSTSP register */
114 #define OTG_GRXSTSP_EPNUM GENMASK(3, 0)
115 #define OTG_GRXSTSP_BCNT GENMASK(14, 4)
116 #define OTG_GRXSTSP_BCNT_SHIFT 4U
117 #define OTG_GRXSTSP_PKTSTS GENMASK(20, 17)
118 #define OTG_GRXSTSP_PKTSTS_SHIFT 17U
119
120 #define STS_GOUT_NAK 1U
121 #define STS_DATA_UPDT 2U
122 #define STS_XFER_COMP 3U
123 #define STS_SETUP_COMP 4U
124 #define STS_SETUP_UPDT 6U
125
126 /* Bit definitions for OTG_GLPMCFG register */
127 #define OTG_GLPMCFG_BESL GENMASK(5, 2)
128
129 /* Bit definitions for OTG_DCFG register */
130 #define OTG_DCFG_DAD GENMASK(10, 4)
131 #define OTG_DCFG_DAD_SHIFT 4U
132
133 /* Bit definitions for OTG_DCTL register */
134 #define OTG_DCTL_RWUSIG BIT(0)
135 #define OTG_DCTL_SDIS BIT(1)
136 #define OTG_DCTL_CGINAK BIT(8)
137
138 /* Bit definitions for OTG_DSTS register */
139 #define OTG_DSTS_SUSPSTS BIT(0)
140 #define OTG_DSTS_ENUMSPD_MASK GENMASK(2, 1)
141 #define OTG_DSTS_FNSOF0 BIT(8)
142
143 #define OTG_DSTS_ENUMSPD(val) ((val) << 1)
144 #define OTG_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ OTG_DSTS_ENUMSPD(0U)
145 #define OTG_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ OTG_DSTS_ENUMSPD(1U)
146 #define OTG_DSTS_ENUMSPD_LS_PHY_6MHZ OTG_DSTS_ENUMSPD(2U)
147 #define OTG_DSTS_ENUMSPD_FS_PHY_48MHZ OTG_DSTS_ENUMSPD(3U)
148
149 /* Bit definitions for OTG_DIEPMSK register */
150 #define OTG_DIEPMSK_XFRCM BIT(0)
151 #define OTG_DIEPMSK_EPDM BIT(1)
152 #define OTG_DIEPMSK_TOM BIT(3)
153
154 /* Bit definitions for OTG_DOEPMSK register */
155 #define OTG_DOEPMSK_XFRCM BIT(0)
156 #define OTG_DOEPMSK_EPDM BIT(1)
157 #define OTG_DOEPMSK_STUPM BIT(3)
158
159 /* Bit definitions for OTG_DIEPCTLx registers */
160 #define OTG_DIEPCTL_MPSIZ GENMASK(10, 0)
161 #define OTG_DIEPCTL_STALL BIT(21)
162 #define OTG_DIEPCTL_CNAK BIT(26)
163 #define OTG_DIEPCTL_SD0PID_SEVNFRM BIT(28)
164 #define OTG_DIEPCTL_SODDFRM BIT(29)
165 #define OTG_DIEPCTL_EPDIS BIT(30)
166 #define OTG_DIEPCTL_EPENA BIT(31)
167
168 /* Bit definitions for OTG_DIEPINTx registers */
169 #define OTG_DIEPINT_XFRC BIT(0)
170 #define OTG_DIEPINT_EPDISD BIT(1)
171 #define OTG_DIEPINT_TOC BIT(3)
172 #define OTG_DIEPINT_ITTXFE BIT(4)
173 #define OTG_DIEPINT_INEPNE BIT(6)
174 #define OTG_DIEPINT_TXFE BIT(7)
175 #define OTG_DIEPINT_TXFE_SHIFT 7U
176
177 #define OTG_DIEPINT_MASK (BIT(13) | BIT(11) | GENMASK(9, 0))
178
179 /* Bit definitions for OTG_DIEPTSIZx registers */
180 #define OTG_DIEPTSIZ_XFRSIZ GENMASK(18, 0)
181 #define OTG_DIEPTSIZ_PKTCNT GENMASK(28, 19)
182 #define OTG_DIEPTSIZ_PKTCNT_SHIFT 19U
183 #define OTG_DIEPTSIZ_MCNT_MASK GENMASK(30, 29)
184 #define OTG_DIEPTSIZ_MCNT_DATA0 BIT(29)
185
186 #define OTG_DIEPTSIZ_PKTCNT_1 BIT(19)
187
188 /* Bit definitions for OTG_DTXFSTSx registers */
189 #define OTG_DTXFSTS_INEPTFSAV GENMASK(15, 0)
190
191 /* Bit definitions for OTG_DOEPCTLx registers */
192 #define OTG_DOEPCTL_STALL BIT(21)
193 #define OTG_DOEPCTL_CNAK BIT(26)
194 #define OTG_DOEPCTL_SD0PID_SEVNFRM BIT(28) /* other than endpoint 0 */
195 #define OTG_DOEPCTL_SD1PID_SODDFRM BIT(29) /* other than endpoint 0 */
196 #define OTG_DOEPCTL_EPDIS BIT(30)
197 #define OTG_DOEPCTL_EPENA BIT(31)
198
199 /* Bit definitions for OTG_DOEPTSIZx registers */
200 #define OTG_DOEPTSIZ_XFRSIZ GENMASK(18, 0)
201 #define OTG_DOEPTSIZ_PKTCNT GENMASK(28, 19)
202 #define OTG_DOEPTSIZ_RXDPID_STUPCNT GENMASK(30, 29)
203
204 /* Bit definitions for OTG_DOEPINTx registers */
205 #define OTG_DOEPINT_XFRC BIT(0)
206 #define OTG_DOEPINT_STUP BIT(3)
207 #define OTG_DOEPINT_OTEPDIS BIT(4)
208
209 #define OTG_DOEPINT_MASK (GENMASK(15, 12) | GENMASK(9, 8) | GENMASK(6, 0))
210
211 #define EP_NB 15U
212 #define EP_ALL 0x10U
213
214 /*
215 * Flush TX FIFO.
216 * handle: PCD handle.
217 * num: FIFO number.
218 * This parameter can be a value from 1 to 15 or EP_ALL.
219 * EP_ALL= 0x10 means Flush all TX FIFOs
220 * return: USB status.
221 */
usb_dwc2_flush_tx_fifo(void * handle,uint32_t num)222 static enum usb_status usb_dwc2_flush_tx_fifo(void *handle, uint32_t num)
223 {
224 uintptr_t usb_base_addr = (uintptr_t)handle;
225 uint64_t timeout = timeout_init_us(USBD_FIFO_FLUSH_TIMEOUT_US);
226
227 mmio_write_32(usb_base_addr + OTG_GRSTCTL,
228 OTG_GRSTCTL_TXFFLSH | (uint32_t)(num << OTG_GRSTCTL_TXFNUM_SHIFT));
229
230 while ((mmio_read_32(usb_base_addr + OTG_GRSTCTL) &
231 OTG_GRSTCTL_TXFFLSH) == OTG_GRSTCTL_TXFFLSH) {
232 if (timeout_elapsed(timeout)) {
233 return USBD_TIMEOUT;
234 }
235 }
236
237 return USBD_OK;
238 }
239
240 /*
241 * Flush RX FIFO.
242 * handle: PCD handle.
243 * return: USB status.
244 */
usb_dwc2_flush_rx_fifo(void * handle)245 static enum usb_status usb_dwc2_flush_rx_fifo(void *handle)
246 {
247 uintptr_t usb_base_addr = (uintptr_t)handle;
248 uint64_t timeout = timeout_init_us(USBD_FIFO_FLUSH_TIMEOUT_US);
249
250 mmio_write_32(usb_base_addr + OTG_GRSTCTL, OTG_GRSTCTL_RXFFLSH);
251
252 while ((mmio_read_32(usb_base_addr + OTG_GRSTCTL) &
253 OTG_GRSTCTL_RXFFLSH) == OTG_GRSTCTL_RXFFLSH) {
254 if (timeout_elapsed(timeout)) {
255 return USBD_TIMEOUT;
256 }
257 }
258
259 return USBD_OK;
260 }
261
262 /*
263 * Return the global USB interrupt status.
264 * handle: PCD handle.
265 * return: Interrupt register value.
266 */
usb_dwc2_read_int(void * handle)267 static uint32_t usb_dwc2_read_int(void *handle)
268 {
269 uintptr_t usb_base_addr = (uintptr_t)handle;
270
271 return mmio_read_32(usb_base_addr + OTG_GINTSTS) &
272 mmio_read_32(usb_base_addr + OTG_GINTMSK);
273 }
274
275 /*
276 * Return the USB device OUT endpoints interrupt.
277 * handle: PCD handle.
278 * return: Device OUT endpoint interrupts.
279 */
usb_dwc2_all_out_ep_int(void * handle)280 static uint32_t usb_dwc2_all_out_ep_int(void *handle)
281 {
282 uintptr_t usb_base_addr = (uintptr_t)handle;
283
284 return ((mmio_read_32(usb_base_addr + OTG_DAINT) &
285 mmio_read_32(usb_base_addr + OTG_DAINTMSK)) &
286 OTG_DAINT_OUT_MASK) >> OTG_DAINT_OUT_SHIFT;
287 }
288
289 /*
290 * Return the USB device IN endpoints interrupt.
291 * handle: PCD handle.
292 * return: Device IN endpoint interrupts.
293 */
usb_dwc2_all_in_ep_int(void * handle)294 static uint32_t usb_dwc2_all_in_ep_int(void *handle)
295 {
296 uintptr_t usb_base_addr = (uintptr_t)handle;
297
298 return ((mmio_read_32(usb_base_addr + OTG_DAINT) &
299 mmio_read_32(usb_base_addr + OTG_DAINTMSK)) &
300 OTG_DAINT_IN_MASK) >> OTG_DAINT_IN_SHIFT;
301 }
302
303 /*
304 * Return Device OUT EP interrupt register.
305 * handle: PCD handle.
306 * epnum: Endpoint number.
307 * This parameter can be a value from 0 to 15.
308 * return: Device OUT EP Interrupt register.
309 */
usb_dwc2_out_ep_int(void * handle,uint8_t epnum)310 static uint32_t usb_dwc2_out_ep_int(void *handle, uint8_t epnum)
311 {
312 uintptr_t usb_base_addr = (uintptr_t)handle;
313
314 return mmio_read_32(usb_base_addr + OTG_DOEP_BASE +
315 (epnum * OTG_DOEP_SIZE) + OTG_DOEPINT) &
316 mmio_read_32(usb_base_addr + OTG_DOEPMSK);
317 }
318
319 /*
320 * Return Device IN EP interrupt register.
321 * handle: PCD handle.
322 * epnum: Endpoint number.
323 * This parameter can be a value from 0 to 15.
324 * return: Device IN EP Interrupt register.
325 */
usb_dwc2_in_ep_int(void * handle,uint8_t epnum)326 static uint32_t usb_dwc2_in_ep_int(void *handle, uint8_t epnum)
327 {
328 uintptr_t usb_base_addr = (uintptr_t)handle;
329 uint32_t msk;
330 uint32_t emp;
331
332 msk = mmio_read_32(usb_base_addr + OTG_DIEPMSK);
333 emp = mmio_read_32(usb_base_addr + OTG_DIEPEMPMSK);
334 msk |= ((emp >> epnum) << OTG_DIEPINT_TXFE_SHIFT) & OTG_DIEPINT_TXFE;
335
336 return mmio_read_32(usb_base_addr + OTG_DIEP_BASE +
337 (epnum * OTG_DIEP_SIZE) + OTG_DIEPINT) & msk;
338 }
339
340 /*
341 * Return USB core mode.
342 * handle: PCD handle.
343 * return: Core mode.
344 * This parameter can be 0 (host) or 1 (device).
345 */
usb_dwc2_get_mode(void * handle)346 static uint32_t usb_dwc2_get_mode(void *handle)
347 {
348 uintptr_t usb_base_addr = (uintptr_t)handle;
349
350 return mmio_read_32(usb_base_addr + OTG_GINTSTS) & OTG_GINTSTS_CMOD;
351 }
352
353 /*
354 * Activate EP0 for detup transactions.
355 * handle: PCD handle.
356 * return: USB status.
357 */
usb_dwc2_activate_setup(void * handle)358 static enum usb_status usb_dwc2_activate_setup(void *handle)
359 {
360 uintptr_t usb_base_addr = (uintptr_t)handle;
361 uintptr_t reg_offset = usb_base_addr + OTG_DIEP_BASE;
362
363 /* Set the MPS of the IN EP based on the enumeration speed */
364 mmio_clrbits_32(reg_offset + OTG_DIEPCTL, OTG_DIEPCTL_MPSIZ);
365
366 if ((mmio_read_32(usb_base_addr + OTG_DSTS) & OTG_DSTS_ENUMSPD_MASK) ==
367 OTG_DSTS_ENUMSPD_LS_PHY_6MHZ) {
368 mmio_setbits_32(reg_offset + OTG_DIEPCTL, 3U);
369 }
370
371 mmio_setbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_CGINAK);
372
373 return USBD_OK;
374 }
375
376 /*
377 * Prepare the EP0 to start the first control setup.
378 * handle: Selected device.
379 * return: USB status.
380 */
usb_dwc2_ep0_out_start(void * handle)381 static enum usb_status usb_dwc2_ep0_out_start(void *handle)
382 {
383 uintptr_t usb_base_addr = (uintptr_t)handle;
384 uintptr_t reg_offset = usb_base_addr + OTG_DIEP_BASE + OTG_DIEPTSIZ;
385 uint32_t reg_value = 0U;
386
387 /* PKTCNT = 1 and XFRSIZ = 24 bytes for endpoint 0 */
388 reg_value |= OTG_DIEPTSIZ_PKTCNT_1;
389 reg_value |= (EP0_FIFO_SIZE & OTG_DIEPTSIZ_XFRSIZ);
390 reg_value |= OTG_DOEPTSIZ_RXDPID_STUPCNT;
391
392 mmio_write_32(reg_offset, reg_value);
393
394 return USBD_OK;
395 }
396
397 /*
398 * Write a packet into the TX FIFO associated with the EP/channel.
399 * handle: Selected device.
400 * src: Pointer to source buffer.
401 * ch_ep_num: Endpoint or host channel number.
402 * len: Number of bytes to write.
403 * return: USB status.
404 */
usb_dwc2_write_packet(void * handle,uint8_t * src,uint8_t ch_ep_num,uint16_t len)405 static enum usb_status usb_dwc2_write_packet(void *handle, uint8_t *src,
406 uint8_t ch_ep_num, uint16_t len)
407 {
408 uint32_t reg_offset;
409 uint32_t count32b = (len + 3U) / 4U;
410 uint32_t i;
411
412 reg_offset = (uintptr_t)handle + OTG_FIFO_BASE +
413 (ch_ep_num * OTG_FIFO_SIZE);
414
415 for (i = 0U; i < count32b; i++) {
416 uint32_t src_copy = 0U;
417 uint32_t j;
418
419 /* Data written to FIFO need to be 4 bytes aligned */
420 for (j = 0U; j < 4U; j++) {
421 src_copy += (*(src + j)) << (8U * j);
422 }
423
424 mmio_write_32(reg_offset, src_copy);
425 src += 4U;
426 }
427
428 return USBD_OK;
429 }
430
431 /*
432 * Read a packet from the RX FIFO associated with the EP/channel.
433 * handle: Selected device.
434 * dst: Destination pointer.
435 * len: Number of bytes to read.
436 * return: Pointer to destination buffer.
437 */
usb_dwc2_read_packet(void * handle,uint8_t * dest,uint16_t len)438 static void *usb_dwc2_read_packet(void *handle, uint8_t *dest, uint16_t len)
439 {
440 uint32_t reg_offset;
441 uint32_t count32b = (len + 3U) / 4U;
442 uint32_t i;
443
444 VERBOSE("read packet length %i to 0x%lx\n", len, (uintptr_t)dest);
445
446 reg_offset = (uintptr_t)handle + OTG_FIFO_BASE;
447
448 for (i = 0U; i < count32b; i++) {
449 *(uint32_t *)dest = mmio_read_32(reg_offset);
450 dest += 4U;
451 dsb();
452 }
453
454 return (void *)dest;
455 }
456
457 /*
458 * Setup and start a transfer over an EP.
459 * handle: Selected device
460 * ep: Pointer to endpoint structure.
461 * return: USB status.
462 */
usb_dwc2_ep_start_xfer(void * handle,struct usbd_ep * ep)463 static enum usb_status usb_dwc2_ep_start_xfer(void *handle, struct usbd_ep *ep)
464 {
465 uintptr_t usb_base_addr = (uintptr_t)handle;
466 uint32_t reg_offset;
467 uint32_t reg_value;
468 uint32_t clear_value;
469
470 if (ep->is_in) {
471 reg_offset = usb_base_addr + OTG_DIEP_BASE + (ep->num * OTG_DIEP_SIZE);
472 clear_value = OTG_DIEPTSIZ_PKTCNT | OTG_DIEPTSIZ_XFRSIZ;
473 if (ep->xfer_len == 0U) {
474 reg_value = OTG_DIEPTSIZ_PKTCNT_1;
475 } else {
476 /*
477 * Program the transfer size and packet count
478 * as follows:
479 * xfersize = N * maxpacket + short_packet
480 * pktcnt = N + (short_packet exist ? 1 : 0)
481 */
482 reg_value = (OTG_DIEPTSIZ_PKTCNT &
483 (((ep->xfer_len + ep->maxpacket - 1U) /
484 ep->maxpacket) << OTG_DIEPTSIZ_PKTCNT_SHIFT))
485 | ep->xfer_len;
486
487 if (ep->type == EP_TYPE_ISOC) {
488 clear_value |= OTG_DIEPTSIZ_MCNT_MASK;
489 reg_value |= OTG_DIEPTSIZ_MCNT_DATA0;
490 }
491 }
492
493 mmio_clrsetbits_32(reg_offset + OTG_DIEPTSIZ, clear_value, reg_value);
494
495 if ((ep->type != EP_TYPE_ISOC) && (ep->xfer_len > 0U)) {
496 /* Enable the TX FIFO empty interrupt for this EP */
497 mmio_setbits_32(usb_base_addr + OTG_DIEPEMPMSK, BIT(ep->num));
498 }
499
500 /* EP enable, IN data in FIFO */
501 reg_value = OTG_DIEPCTL_CNAK | OTG_DIEPCTL_EPENA;
502
503 if (ep->type == EP_TYPE_ISOC) {
504 if ((mmio_read_32(usb_base_addr + OTG_DSTS) & OTG_DSTS_FNSOF0) == 0U) {
505 reg_value |= OTG_DIEPCTL_SODDFRM;
506 } else {
507 reg_value |= OTG_DIEPCTL_SD0PID_SEVNFRM;
508 }
509 }
510
511 mmio_setbits_32(reg_offset + OTG_DIEPCTL, reg_value);
512
513 if (ep->type == EP_TYPE_ISOC) {
514 usb_dwc2_write_packet(handle, ep->xfer_buff, ep->num, ep->xfer_len);
515 }
516 } else {
517 reg_offset = usb_base_addr + OTG_DOEP_BASE + (ep->num * OTG_DOEP_SIZE);
518 /*
519 * Program the transfer size and packet count as follows:
520 * pktcnt = N
521 * xfersize = N * maxpacket
522 */
523 if (ep->xfer_len == 0U) {
524 reg_value = ep->maxpacket | OTG_DIEPTSIZ_PKTCNT_1;
525 } else {
526 uint16_t pktcnt = (ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket;
527
528 reg_value = (pktcnt << OTG_DIEPTSIZ_PKTCNT_SHIFT) |
529 (ep->maxpacket * pktcnt);
530 }
531
532 mmio_clrsetbits_32(reg_offset + OTG_DOEPTSIZ,
533 OTG_DOEPTSIZ_XFRSIZ & OTG_DOEPTSIZ_PKTCNT,
534 reg_value);
535
536 /* EP enable */
537 reg_value = OTG_DOEPCTL_CNAK | OTG_DOEPCTL_EPENA;
538
539 if (ep->type == EP_TYPE_ISOC) {
540 if ((mmio_read_32(usb_base_addr + OTG_DSTS) & OTG_DSTS_FNSOF0) == 0U) {
541 reg_value |= OTG_DOEPCTL_SD1PID_SODDFRM;
542 } else {
543 reg_value |= OTG_DOEPCTL_SD0PID_SEVNFRM;
544 }
545 }
546
547 mmio_setbits_32(reg_offset + OTG_DOEPCTL, reg_value);
548 }
549
550 return USBD_OK;
551 }
552
553 /*
554 * Setup and start a transfer over the EP0.
555 * handle: Selected device.
556 * ep: Pointer to endpoint structure.
557 * return: USB status.
558 */
usb_dwc2_ep0_start_xfer(void * handle,struct usbd_ep * ep)559 static enum usb_status usb_dwc2_ep0_start_xfer(void *handle, struct usbd_ep *ep)
560 {
561 uintptr_t usb_base_addr = (uintptr_t)handle;
562 uint32_t reg_offset;
563 uint32_t reg_value;
564
565 if (ep->is_in) {
566 reg_offset = usb_base_addr + OTG_DIEP_BASE +
567 (ep->num * OTG_DIEP_SIZE);
568
569 if (ep->xfer_len == 0U) {
570 reg_value = OTG_DIEPTSIZ_PKTCNT_1;
571 } else {
572 /*
573 * Program the transfer size and packet count
574 * as follows:
575 * xfersize = N * maxpacket + short_packet
576 * pktcnt = N + (short_packet exist ? 1 : 0)
577 */
578
579 if (ep->xfer_len > ep->maxpacket) {
580 ep->xfer_len = ep->maxpacket;
581 }
582
583 reg_value = OTG_DIEPTSIZ_PKTCNT_1 | ep->xfer_len;
584 }
585
586 mmio_clrsetbits_32(reg_offset + OTG_DIEPTSIZ,
587 OTG_DIEPTSIZ_XFRSIZ | OTG_DIEPTSIZ_PKTCNT,
588 reg_value);
589
590 /* Enable the TX FIFO empty interrupt for this EP */
591 if (ep->xfer_len > 0U) {
592 mmio_setbits_32(usb_base_addr + OTG_DIEPEMPMSK,
593 BIT(ep->num));
594 }
595
596 /* EP enable, IN data in FIFO */
597 mmio_setbits_32(reg_offset + OTG_DIEPCTL,
598 OTG_DIEPCTL_CNAK | OTG_DIEPCTL_EPENA);
599 } else {
600 reg_offset = usb_base_addr + OTG_DOEP_BASE +
601 (ep->num * OTG_DOEP_SIZE);
602
603 /*
604 * Program the transfer size and packet count as follows:
605 * pktcnt = N
606 * xfersize = N * maxpacket
607 */
608 if (ep->xfer_len > 0U) {
609 ep->xfer_len = ep->maxpacket;
610 }
611
612 reg_value = OTG_DIEPTSIZ_PKTCNT_1 | ep->maxpacket;
613
614 mmio_clrsetbits_32(reg_offset + OTG_DIEPTSIZ,
615 OTG_DIEPTSIZ_XFRSIZ | OTG_DIEPTSIZ_PKTCNT,
616 reg_value);
617
618 /* EP enable */
619 mmio_setbits_32(reg_offset + OTG_DOEPCTL,
620 OTG_DOEPCTL_CNAK | OTG_DOEPCTL_EPENA);
621 }
622
623 return USBD_OK;
624 }
625
626 /*
627 * Set a stall condition over an EP.
628 * handle: Selected device.
629 * ep: Pointer to endpoint structure.
630 * return: USB status.
631 */
usb_dwc2_ep_set_stall(void * handle,struct usbd_ep * ep)632 static enum usb_status usb_dwc2_ep_set_stall(void *handle, struct usbd_ep *ep)
633 {
634 uintptr_t usb_base_addr = (uintptr_t)handle;
635 uint32_t reg_offset;
636 uint32_t reg_value;
637
638 if (ep->is_in) {
639 reg_offset = usb_base_addr + OTG_DIEP_BASE +
640 (ep->num * OTG_DIEP_SIZE);
641 reg_value = mmio_read_32(reg_offset + OTG_DIEPCTL);
642
643 if ((reg_value & OTG_DIEPCTL_EPENA) == 0U) {
644 reg_value &= ~OTG_DIEPCTL_EPDIS;
645 }
646
647 reg_value |= OTG_DIEPCTL_STALL;
648
649 mmio_write_32(reg_offset + OTG_DIEPCTL, reg_value);
650 } else {
651 reg_offset = usb_base_addr + OTG_DOEP_BASE +
652 (ep->num * OTG_DOEP_SIZE);
653 reg_value = mmio_read_32(reg_offset + OTG_DOEPCTL);
654
655 if ((reg_value & OTG_DOEPCTL_EPENA) == 0U) {
656 reg_value &= ~OTG_DOEPCTL_EPDIS;
657 }
658
659 reg_value |= OTG_DOEPCTL_STALL;
660
661 mmio_write_32(reg_offset + OTG_DOEPCTL, reg_value);
662 }
663
664 return USBD_OK;
665 }
666
667 /*
668 * Stop the USB device mode.
669 * handle: Selected device.
670 * return: USB status.
671 */
usb_dwc2_stop_device(void * handle)672 static enum usb_status usb_dwc2_stop_device(void *handle)
673 {
674 uintptr_t usb_base_addr = (uintptr_t)handle;
675 uint32_t i;
676
677 /* Disable Int */
678 mmio_clrbits_32(usb_base_addr + OTG_GAHBCFG, OTG_GAHBCFG_GINT);
679
680 /* Clear pending interrupts */
681 for (i = 0U; i < EP_NB; i++) {
682 mmio_write_32(usb_base_addr + OTG_DIEP_BASE + (i * OTG_DIEP_SIZE) + OTG_DIEPINT,
683 OTG_DIEPINT_MASK);
684 mmio_write_32(usb_base_addr + OTG_DOEP_BASE + (i * OTG_DOEP_SIZE) + OTG_DOEPINT,
685 OTG_DOEPINT_MASK);
686 }
687
688 mmio_write_32(usb_base_addr + OTG_DAINT, OTG_DAINT_IN_MASK | OTG_DAINT_OUT_MASK);
689
690 /* Clear interrupt masks */
691 mmio_write_32(usb_base_addr + OTG_DIEPMSK, 0U);
692 mmio_write_32(usb_base_addr + OTG_DOEPMSK, 0U);
693 mmio_write_32(usb_base_addr + OTG_DAINTMSK, 0U);
694
695 /* Flush the FIFO */
696 usb_dwc2_flush_rx_fifo(handle);
697 usb_dwc2_flush_tx_fifo(handle, EP_ALL);
698
699 /* Disconnect the USB device by disabling the pull-up/pull-down */
700 mmio_setbits_32((uintptr_t)handle + OTG_DCTL, OTG_DCTL_SDIS);
701
702 return USBD_OK;
703 }
704
705 /*
706 * Stop the USB device mode.
707 * handle: Selected device.
708 * address: New device address to be assigned.
709 * This parameter can be a value from 0 to 255.
710 * return: USB status.
711 */
usb_dwc2_set_address(void * handle,uint8_t address)712 static enum usb_status usb_dwc2_set_address(void *handle, uint8_t address)
713 {
714 uintptr_t usb_base_addr = (uintptr_t)handle;
715
716 mmio_clrsetbits_32(usb_base_addr + OTG_DCFG,
717 OTG_DCFG_DAD,
718 address << OTG_DCFG_DAD_SHIFT);
719
720 return USBD_OK;
721 }
722
723 /*
724 * Check FIFO for the next packet to be loaded.
725 * handle: Selected device.
726 * epnum : Endpoint number.
727 * xfer_len: Block length.
728 * xfer_count: Number of blocks.
729 * maxpacket: Max packet length.
730 * xfer_buff: Buffer pointer.
731 * return: USB status.
732 */
usb_dwc2_write_empty_tx_fifo(void * handle,uint32_t epnum,uint32_t xfer_len,uint32_t * xfer_count,uint32_t maxpacket,uint8_t ** xfer_buff)733 static enum usb_status usb_dwc2_write_empty_tx_fifo(void *handle,
734 uint32_t epnum,
735 uint32_t xfer_len,
736 uint32_t *xfer_count,
737 uint32_t maxpacket,
738 uint8_t **xfer_buff)
739 {
740 uintptr_t usb_base_addr = (uintptr_t)handle;
741 uint32_t reg_offset;
742 int32_t len;
743 uint32_t len32b;
744 enum usb_status ret;
745
746 len = xfer_len - *xfer_count;
747
748 if ((len > 0) && ((uint32_t)len > maxpacket)) {
749 len = maxpacket;
750 }
751
752 len32b = (len + 3U) / 4U;
753
754 reg_offset = usb_base_addr + OTG_DIEP_BASE + (epnum * OTG_DIEP_SIZE);
755
756 while (((mmio_read_32(reg_offset + OTG_DTXFSTS) &
757 OTG_DTXFSTS_INEPTFSAV) > len32b) &&
758 (*xfer_count < xfer_len) && (xfer_len != 0U)) {
759 /* Write the FIFO */
760 len = xfer_len - *xfer_count;
761
762 if ((len > 0) && ((uint32_t)len > maxpacket)) {
763 len = maxpacket;
764 }
765
766 len32b = (len + 3U) / 4U;
767
768 ret = usb_dwc2_write_packet(handle, *xfer_buff, epnum, len);
769 if (ret != USBD_OK) {
770 return ret;
771 }
772
773 *xfer_buff += len;
774 *xfer_count += len;
775 }
776
777 if (len <= 0) {
778 mmio_clrbits_32(usb_base_addr + OTG_DIEPEMPMSK, BIT(epnum));
779 }
780
781 return USBD_OK;
782 }
783
784 /*
785 * Handle PCD interrupt request.
786 * handle: PCD handle.
787 * param: Pointer to information updated by the IT handling.
788 * return: Action to do after IT handling.
789 */
usb_dwc2_it_handler(void * handle,uint32_t * param)790 static enum usb_action usb_dwc2_it_handler(void *handle, uint32_t *param)
791 {
792 uintptr_t usb_base_addr = (uintptr_t)handle;
793 uint32_t ep_intr;
794 uint32_t epint;
795 uint32_t epnum;
796 uint32_t temp;
797 enum usb_status ret;
798
799 if (usb_dwc2_get_mode(handle) != USB_OTG_MODE_DEVICE) {
800 return USB_NOTHING;
801 }
802
803 /* Avoid spurious interrupt */
804 if (usb_dwc2_read_int(handle) == 0U) {
805 return USB_NOTHING;
806 }
807
808 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_MMIS) != 0U) {
809 /* Incorrect mode, acknowledge the interrupt */
810 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_MMIS);
811 }
812
813 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_OEPINT) != 0U) {
814 uint32_t reg_offset;
815
816 /* Read in the device interrupt bits */
817 ep_intr = usb_dwc2_all_out_ep_int(handle);
818 epnum = 0U;
819 while ((ep_intr & BIT(0)) != BIT(0)) {
820 epnum++;
821 ep_intr >>= 1;
822 }
823
824 reg_offset = usb_base_addr + OTG_DOEP_BASE + (epnum * OTG_DOEP_SIZE) + OTG_DOEPINT;
825
826 epint = usb_dwc2_out_ep_int(handle, epnum);
827
828 if ((epint & OTG_DOEPINT_XFRC) == OTG_DOEPINT_XFRC) {
829 mmio_write_32(reg_offset, OTG_DOEPINT_XFRC);
830 *param = epnum;
831
832 return USB_DATA_OUT;
833 }
834
835 if ((epint & OTG_DOEPINT_STUP) == OTG_DOEPINT_STUP) {
836 /* Inform that a setup packet is available */
837 mmio_write_32(reg_offset, OTG_DOEPINT_STUP);
838
839 return USB_SETUP;
840 }
841
842 if ((epint & OTG_DOEPINT_OTEPDIS) == OTG_DOEPINT_OTEPDIS) {
843 mmio_write_32(reg_offset, OTG_DOEPINT_OTEPDIS);
844 }
845 }
846
847 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_IEPINT) != 0U) {
848 uint32_t reg_offset;
849
850 /* Read in the device interrupt bits */
851 ep_intr = usb_dwc2_all_in_ep_int(handle);
852 epnum = 0U;
853 while ((ep_intr & BIT(0)) != BIT(0)) {
854 epnum++;
855 ep_intr >>= 1;
856 }
857
858 reg_offset = usb_base_addr + OTG_DIEP_BASE + (epnum * OTG_DIEP_SIZE) + OTG_DIEPINT;
859
860 epint = usb_dwc2_in_ep_int(handle, epnum);
861
862 if ((epint & OTG_DIEPINT_XFRC) == OTG_DIEPINT_XFRC) {
863 mmio_clrbits_32(usb_base_addr + OTG_DIEPEMPMSK, BIT(epnum));
864 mmio_write_32(reg_offset, OTG_DIEPINT_XFRC);
865 *param = epnum;
866
867 return USB_DATA_IN;
868 }
869
870 if ((epint & OTG_DIEPINT_TOC) == OTG_DIEPINT_TOC) {
871 mmio_write_32(reg_offset, OTG_DIEPINT_TOC);
872 }
873
874 if ((epint & OTG_DIEPINT_ITTXFE) == OTG_DIEPINT_ITTXFE) {
875 mmio_write_32(reg_offset, OTG_DIEPINT_ITTXFE);
876 }
877
878 if ((epint & OTG_DIEPINT_INEPNE) == OTG_DIEPINT_INEPNE) {
879 mmio_write_32(reg_offset, OTG_DIEPINT_INEPNE);
880 }
881
882 if ((epint & OTG_DIEPINT_EPDISD) == OTG_DIEPINT_EPDISD) {
883 mmio_write_32(reg_offset, OTG_DIEPINT_EPDISD);
884 }
885
886 if ((epint & OTG_DIEPINT_TXFE) == OTG_DIEPINT_TXFE) {
887 *param = epnum;
888
889 return USB_WRITE_EMPTY;
890 }
891 }
892
893 /* Handle resume interrupt */
894 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_WKUPINT) != 0U) {
895 INFO("handle USB : Resume\n");
896
897 /* Clear the remote wake-up signaling */
898 mmio_clrbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_RWUSIG);
899 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_WKUPINT);
900
901 return USB_RESUME;
902 }
903
904 /* Handle suspend interrupt */
905 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_USBSUSP) != 0U) {
906 INFO("handle USB : Suspend int\n");
907
908 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_USBSUSP);
909
910 if ((mmio_read_32(usb_base_addr + OTG_DSTS) &
911 OTG_DSTS_SUSPSTS) == OTG_DSTS_SUSPSTS) {
912 return USB_SUSPEND;
913 }
914 }
915
916 /* Handle LPM interrupt */
917 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_LPMINT) != 0U) {
918 INFO("handle USB : LPM int enter in suspend\n");
919
920 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_LPMINT);
921 *param = (mmio_read_32(usb_base_addr + OTG_GLPMCFG) &
922 OTG_GLPMCFG_BESL) >> 2;
923
924 return USB_LPM;
925 }
926
927 /* Handle reset interrupt */
928 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_USBRST) != 0U) {
929 INFO("handle USB : Reset\n");
930
931 mmio_clrbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_RWUSIG);
932
933 usb_dwc2_flush_tx_fifo(handle, 0U);
934
935 mmio_write_32(usb_base_addr + OTG_DAINT, OTG_DAINT_IN_MASK | OTG_DAINT_OUT_MASK);
936 mmio_setbits_32(usb_base_addr + OTG_DAINTMSK, OTG_DAINT_EP0_IN | OTG_DAINT_EP0_OUT);
937
938 mmio_setbits_32(usb_base_addr + OTG_DOEPMSK, OTG_DOEPMSK_STUPM |
939 OTG_DOEPMSK_XFRCM |
940 OTG_DOEPMSK_EPDM);
941 mmio_setbits_32(usb_base_addr + OTG_DIEPMSK, OTG_DIEPMSK_TOM |
942 OTG_DIEPMSK_XFRCM |
943 OTG_DIEPMSK_EPDM);
944
945 /* Set default address to 0 */
946 mmio_clrbits_32(usb_base_addr + OTG_DCFG, OTG_DCFG_DAD);
947
948 /* Setup EP0 to receive SETUP packets */
949 ret = usb_dwc2_ep0_out_start(handle);
950 if (ret != USBD_OK) {
951 return ret;
952 }
953
954 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_USBRST);
955
956 return USB_RESET;
957 }
958
959 /* Handle enumeration done interrupt */
960 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_ENUMDNE) != 0U) {
961 ret = usb_dwc2_activate_setup(handle);
962 if (ret != USBD_OK) {
963 return ret;
964 }
965
966 mmio_clrbits_32(usb_base_addr + OTG_GUSBCFG, OTG_GUSBCFG_TRDT);
967
968 mmio_setbits_32(usb_base_addr + OTG_GUSBCFG,
969 (USBD_HS_TRDT_VALUE << OTG_GUSBCFG_TRDT_SHIFT) & OTG_GUSBCFG_TRDT);
970
971 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_ENUMDNE);
972
973 return USB_ENUM_DONE;
974 }
975
976 /* Handle RXQLevel interrupt */
977 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_RXFLVL) != 0U) {
978 mmio_clrbits_32(usb_base_addr + OTG_GINTMSK,
979 OTG_GINTSTS_RXFLVL);
980
981 temp = mmio_read_32(usb_base_addr + OTG_GRXSTSP);
982
983 *param = temp & OTG_GRXSTSP_EPNUM;
984 *param |= (temp & OTG_GRXSTSP_BCNT) << (USBD_OUT_COUNT_SHIFT -
985 OTG_GRXSTSP_BCNT_SHIFT);
986
987 if (((temp & OTG_GRXSTSP_PKTSTS) >> OTG_GRXSTSP_PKTSTS_SHIFT) == STS_DATA_UPDT) {
988 if ((temp & OTG_GRXSTSP_BCNT) != 0U) {
989 mmio_setbits_32(usb_base_addr + OTG_GINTMSK, OTG_GINTSTS_RXFLVL);
990
991 return USB_READ_DATA_PACKET;
992 }
993 } else if (((temp & OTG_GRXSTSP_PKTSTS) >> OTG_GRXSTSP_PKTSTS_SHIFT) ==
994 STS_SETUP_UPDT) {
995 mmio_setbits_32(usb_base_addr + OTG_GINTMSK, OTG_GINTSTS_RXFLVL);
996
997 return USB_READ_SETUP_PACKET;
998 }
999
1000 mmio_setbits_32(usb_base_addr + OTG_GINTMSK, OTG_GINTSTS_RXFLVL);
1001 }
1002
1003 /* Handle SOF interrupt */
1004 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_SOF) != 0U) {
1005 INFO("handle USB : SOF\n");
1006
1007 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_SOF);
1008
1009 return USB_SOF;
1010 }
1011
1012 /* Handle incomplete ISO IN interrupt */
1013 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_IISOIXFR) != 0U) {
1014 INFO("handle USB : ISO IN\n");
1015
1016 mmio_write_32(usb_base_addr + OTG_GINTSTS,
1017 OTG_GINTSTS_IISOIXFR);
1018 }
1019
1020 /* Handle incomplete ISO OUT interrupt */
1021 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_IPXFR_INCOMPISOOUT) !=
1022 0U) {
1023 INFO("handle USB : ISO OUT\n");
1024
1025 mmio_write_32(usb_base_addr + OTG_GINTSTS,
1026 OTG_GINTSTS_IPXFR_INCOMPISOOUT);
1027 }
1028
1029 /* Handle connection event interrupt */
1030 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_SRQINT) != 0U) {
1031 INFO("handle USB : Connect\n");
1032
1033 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_SRQINT);
1034 }
1035
1036 /* Handle disconnection event interrupt */
1037 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_OTGINT) != 0U) {
1038 INFO("handle USB : Disconnect\n");
1039
1040 temp = mmio_read_32(usb_base_addr + OTG_GOTGINT);
1041
1042 if ((temp & OTG_GOTGINT_SEDET) == OTG_GOTGINT_SEDET) {
1043 return USB_DISCONNECT;
1044 }
1045 }
1046
1047 return USB_NOTHING;
1048 }
1049
1050 /*
1051 * Start the usb device mode
1052 * usb_core_handle: USB core driver handle.
1053 * return USB status.
1054 */
usb_dwc2_start_device(void * handle)1055 static enum usb_status usb_dwc2_start_device(void *handle)
1056 {
1057 uintptr_t usb_base_addr = (uintptr_t)handle;
1058
1059 mmio_clrbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_SDIS);
1060 mmio_setbits_32(usb_base_addr + OTG_GAHBCFG, OTG_GAHBCFG_GINT);
1061
1062 return USBD_OK;
1063 }
1064
1065 static const struct usb_driver usb_dwc2driver = {
1066 .ep0_out_start = usb_dwc2_ep0_out_start,
1067 .ep_start_xfer = usb_dwc2_ep_start_xfer,
1068 .ep0_start_xfer = usb_dwc2_ep0_start_xfer,
1069 .write_packet = usb_dwc2_write_packet,
1070 .read_packet = usb_dwc2_read_packet,
1071 .ep_set_stall = usb_dwc2_ep_set_stall,
1072 .start_device = usb_dwc2_start_device,
1073 .stop_device = usb_dwc2_stop_device,
1074 .set_address = usb_dwc2_set_address,
1075 .write_empty_tx_fifo = usb_dwc2_write_empty_tx_fifo,
1076 .it_handler = usb_dwc2_it_handler
1077 };
1078
1079 /*
1080 * Initialize USB DWC2 driver.
1081 * usb_core_handle: USB core driver handle.
1082 * pcd_handle: PCD handle.
1083 * base_register: USB global register base address.
1084 */
stm32mp1_usb_init_driver(struct usb_handle * usb_core_handle,struct pcd_handle * pcd_handle,void * base_register)1085 void stm32mp1_usb_init_driver(struct usb_handle *usb_core_handle,
1086 struct pcd_handle *pcd_handle,
1087 void *base_register)
1088 {
1089 register_usb_driver(usb_core_handle, pcd_handle, &usb_dwc2driver,
1090 base_register);
1091 }
1092