1/*
2 * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/dts-v1/;
10
11#include "rtsm_ve-motherboard.dtsi"
12
13/ {
14	model = "V2P-CA5s";
15	compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <1>;
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu@0 {
25			device_type = "cpu";
26			compatible = "arm,cortex-a5";
27			reg = <0>;
28		};
29
30	};
31
32	memory@80000000 {
33		device_type = "memory";
34		reg = <0 0x80000000 0x1000000>;
35	};
36
37	reserved-memory {
38		#address-cells = <2>;
39		#size-cells = <1>;
40		ranges;
41
42		/* Chipselect 2,00000000 is physically at 0x18000000 */
43		vram: vram@18000000 {
44			/* 8 MB of designated video RAM */
45			compatible = "shared-dma-pool";
46			reg = <0 0x18000000 0x00800000>;
47			no-map;
48		};
49	};
50
51	hdlcd@2a110000 {
52		compatible = "arm,hdlcd";
53		reg = <0 0x2a110000 0x1000>;
54		interrupts = <0 85 4>;
55		clocks = <&oscclk3>;
56		clock-names = "pxlclk";
57	};
58
59	scu@2c000000 {
60		compatible = "arm,cortex-a5-scu";
61		reg = <0 0x2c000000 0x58>;
62	};
63
64	watchdog@2c000620 {
65		compatible = "arm,cortex-a5-twd-wdt";
66		reg = <0 0x2c000620 0x20>;
67		interrupts = <1 14 0x304>;
68	};
69
70	gic: interrupt-controller@2c001000 {
71		compatible = "arm,cortex-a9-gic";
72		#interrupt-cells = <3>;
73		#address-cells = <0>;
74		interrupt-controller;
75		reg = <0 0x2c001000 0x1000>,
76		      <0 0x2c000100 0x100>;
77	};
78
79	mcc {
80		oscclk0: oscclk0 {
81			/* CPU and internal AXI reference clock */
82			compatible = "arm,vexpress-osc";
83			arm,vexpress-sysreg,func = <1 0>;
84			freq-range = <50000000 100000000>;
85			#clock-cells = <0>;
86			clock-output-names = "oscclk0";
87		};
88
89		oscclk1: oscclk1 {
90			/* Multiplexed AXI master clock */
91			compatible = "arm,vexpress-osc";
92			arm,vexpress-sysreg,func = <1 1>;
93			freq-range = <5000000 50000000>;
94			#clock-cells = <0>;
95			clock-output-names = "oscclk1";
96		};
97
98		oscclk2 {
99			/* DDR2 */
100			compatible = "arm,vexpress-osc";
101			arm,vexpress-sysreg,func = <1 2>;
102			freq-range = <80000000 120000000>;
103			#clock-cells = <0>;
104			clock-output-names = "oscclk2";
105		};
106
107		oscclk3: oscclk3 {
108			/* HDLCD */
109			compatible = "arm,vexpress-osc";
110			arm,vexpress-sysreg,func = <1 3>;
111			freq-range = <23750000 165000000>;
112			#clock-cells = <0>;
113			clock-output-names = "oscclk3";
114		};
115
116		oscclk4 {
117			/* Test chip gate configuration */
118			compatible = "arm,vexpress-osc";
119			arm,vexpress-sysreg,func = <1 4>;
120			freq-range = <80000000 80000000>;
121			#clock-cells = <0>;
122			clock-output-names = "oscclk4";
123		};
124
125		smbclk: oscclk5 {
126			/* SMB clock */
127			compatible = "arm,vexpress-osc";
128			arm,vexpress-sysreg,func = <1 5>;
129			freq-range = <25000000 60000000>;
130			#clock-cells = <0>;
131			clock-output-names = "oscclk5";
132		};
133	};
134
135	panel {
136		compatible = "arm,rtsm-display";
137		port {
138			panel_in: endpoint {
139				remote-endpoint = <&clcd_pads>;
140			};
141		};
142	};
143
144	bus@8000000 {
145		#interrupt-cells = <1>;
146		interrupt-map-mask = <0 0 63>;
147		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
148				<0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
149				<0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
150				<0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
151				<0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
152				<0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
153				<0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
154				<0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
155				<0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
156				<0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
157				<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
158				<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
159				<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
160				<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
161				<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
162				<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
163				<0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
164				<0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
165				<0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
166	};
167};
168