1/*
2 * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/dts-v1/;
10
11#include "rtsm_ve-motherboard.dtsi"
12
13/ {
14	model = "V2F-1XV7 Cortex-A7x1 SMM";
15	compatible = "arm,vexpress,v2f-1xv7", "arm,vexpress";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <1>;
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu@0 {
25			device_type = "cpu";
26			compatible = "arm,cortex-a7";
27			reg = <0>;
28		};
29	};
30
31	memory@0,80000000 {
32		device_type = "memory";
33		reg = <0 0x80000000 0x80000000>; /* 2GB @ 2GB */
34	};
35
36	reserved-memory {
37		#address-cells = <2>;
38		#size-cells = <1>;
39		ranges;
40
41		/* Chipselect 2,00000000 is physically at 0x18000000 */
42		vram: vram@18000000 {
43			/* 8 MB of designated video RAM */
44			compatible = "shared-dma-pool";
45			reg = <0 0x18000000 0x00800000>;
46			no-map;
47		};
48	};
49
50	gic: interrupt-controller@2c001000 {
51		compatible = "arm,cortex-a15-gic";
52		#interrupt-cells = <3>;
53		#address-cells = <0>;
54		interrupt-controller;
55		reg = <0 0x2c001000 0x1000>,
56		      <0 0x2c002000 0x1000>,
57		      <0 0x2c004000 0x2000>,
58		      <0 0x2c006000 0x2000>;
59		interrupts = <1 9 0xf04>;
60	};
61
62	smbclk: refclk24mhzx2 {
63		/* Reference 24MHz clock x 2 */
64		compatible = "fixed-clock";
65		#clock-cells = <0>;
66		clock-frequency = <48000000>;
67		clock-output-names = "smclk";
68	};
69
70	panel {
71		compatible = "arm,rtsm-display";
72		port {
73			panel_in: endpoint {
74				remote-endpoint = <&clcd_pads>;
75			};
76		};
77	};
78
79	bus@8000000 {
80		#interrupt-cells = <1>;
81		interrupt-map-mask = <0 0 63>;
82		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
83				<0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
84				<0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
85				<0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
86				<0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
87				<0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
88				<0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
89				<0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
90				<0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
91				<0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
92				<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
93				<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
94				<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
95				<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
96				<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
97				<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
98				<0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
99				<0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
100				<0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
101	};
102};
103