1/*
2 * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8#include "morello.dtsi"
9
10/ {
11	model = "Arm Morello Fixed Virtual Platform";
12
13	chosen {
14		stdout-path = "serial0:115200n8";
15	};
16
17	reserved-memory {
18		#address-cells = <2>;
19		#size-cells = <2>;
20		ranges;
21
22		secure-firmware@ff000000 {
23			reg = <0 0xff000000 0 0x01000000>;
24			no-map;
25		};
26	};
27
28	cpus {
29		#address-cells = <2>;
30		#size-cells = <0>;
31
32		cpu-map {
33			cluster0 {
34				core0 {
35					cpu = <&CPU0>;
36				};
37				core1 {
38					cpu = <&CPU1>;
39				};
40			};
41			cluster1 {
42				core0 {
43					cpu = <&CPU2>;
44				};
45				core1 {
46					cpu = <&CPU3>;
47				};
48			};
49		};
50		CPU0: cpu0@0 {
51			compatible = "arm,armv8";
52			reg = <0x0 0x0>;
53			device_type = "cpu";
54			enable-method = "psci";
55			clocks = <&scmi_dvfs 0>;
56		};
57		CPU1: cpu1@100 {
58			compatible = "arm,armv8";
59			reg = <0x0 0x100>;
60			device_type = "cpu";
61			enable-method = "psci";
62			clocks = <&scmi_dvfs 0>;
63		};
64		CPU2: cpu2@10000 {
65			compatible = "arm,armv8";
66			reg = <0x0 0x10000>;
67			device_type = "cpu";
68			enable-method = "psci";
69			clocks = <&scmi_dvfs 1>;
70		};
71		CPU3: cpu3@10100 {
72			compatible = "arm,armv8";
73			reg = <0x0 0x10100>;
74			device_type = "cpu";
75			enable-method = "psci";
76			clocks = <&scmi_dvfs 1>;
77		};
78	};
79
80	/* The first bank of memory, memory map is actually provided by UEFI. */
81	memory@80000000 {
82		device_type = "memory";
83		/* [0x80000000-0xffffffff] */
84		reg = <0x00000000 0x80000000 0x0 0x80000000>;
85	};
86
87	memory@8080000000 {
88		device_type = "memory";
89		/* [0x8080000000-0x83ffffffff] */
90		reg = <0x00000080 0x80000000 0x1 0x80000000>;
91	};
92
93	virtio_block@1c170000 {
94		compatible = "virtio,mmio";
95		reg = <0x0 0x1c170000 0x0 0x200>;
96		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
97	};
98
99	virtio_net@1c180000 {
100		compatible = "virtio,mmio";
101		reg = <0x0 0x1c180000 0x0 0x200>;
102		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
103	};
104
105	virtio_rng@1c190000 {
106		compatible = "virtio,mmio";
107		reg = <0x0 0x1c190000 0x0 0x200>;
108		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
109	};
110
111	virtio_p9@1c1a0000 {
112		compatible = "virtio,mmio";
113		reg = <0x0 0x1c1a0000 0x0 0x200>;
114		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
115	};
116
117	ethernet@1d100000 {
118		compatible = "smsc,lan91c111";
119		reg = <0x0 0x1d100000 0x0 0x10000>;
120		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
121	};
122
123	kmi@1c150000 {
124		compatible = "arm,pl050", "arm,primecell";
125		reg = <0x0 0x1c150000 0x0 0x1000>;
126		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
127		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
128		clock-names = "KMIREFCLK", "apb_pclk";
129	};
130
131	kmi@1c160000 {
132		compatible = "arm,pl050", "arm,primecell";
133		reg = <0x0 0x1c160000 0x0 0x1000>;
134		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
135		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
136		clock-names = "KMIREFCLK", "apb_pclk";
137	};
138
139	firmware {
140		scmi {
141			compatible = "arm,scmi";
142			mbox-names = "tx", "rx";
143			mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
144			shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
145			#address-cells = <1>;
146			#size-cells = <0>;
147
148			scmi_dvfs: protocol@13 {
149				reg = <0x13>;
150				#clock-cells = <1>;
151			};
152		};
153	};
154
155	bp_clock24mhz: clock24mhz {
156		compatible = "fixed-clock";
157		#clock-cells = <0>;
158		clock-frequency = <24000000>;
159		clock-output-names = "bp:clock24mhz";
160	};
161};
162
163&gic {
164	reg = <0x0 0x30000000 0 0x10000>,	/* GICD */
165	      <0x0 0x300c0000 0 0x80000>;	/* GICR */
166	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
167};
168