1/*
2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8#include "morello.dtsi"
9
10/ {
11	model = "Arm Morello System Development Platform";
12
13	chosen {
14		stdout-path = "serial0:115200n8";
15	};
16
17	reserved-memory {
18		#address-cells = <2>;
19		#size-cells = <2>;
20		ranges;
21
22		secure-firmware@ff000000 {
23			reg = <0 0xff000000 0 0x01000000>;
24			no-map;
25		};
26	};
27
28	cpus {
29		#address-cells = <2>;
30		#size-cells = <0>;
31		cpu0@0 {
32			compatible = "arm,armv8";
33			reg = <0x0 0x0>;
34			device_type = "cpu";
35			enable-method = "psci";
36			clocks = <&scmi_dvfs 0>;
37		};
38		cpu1@100 {
39			compatible = "arm,armv8";
40			reg = <0x0 0x100>;
41			device_type = "cpu";
42			enable-method = "psci";
43			clocks = <&scmi_dvfs 0>;
44		};
45		cpu2@10000 {
46			compatible = "arm,armv8";
47			reg = <0x0 0x10000>;
48			device_type = "cpu";
49			enable-method = "psci";
50			clocks = <&scmi_dvfs 1>;
51		};
52		cpu3@10100 {
53			compatible = "arm,armv8";
54			reg = <0x0 0x10100>;
55			device_type = "cpu";
56			enable-method = "psci";
57			clocks = <&scmi_dvfs 1>;
58		};
59	};
60
61	/* The first bank of memory, memory map is actually provided by UEFI. */
62	memory@80000000 {
63		device_type = "memory";
64		/* [0x80000000-0xffffffff] */
65		reg = <0x00000000 0x80000000 0x0 0x7F000000>;
66	};
67
68	memory@8080000000 {
69		device_type = "memory";
70		/* [0x8080000000-0x83f7ffffff] */
71		reg = <0x00000080 0x80000000 0x3 0x78000000>;
72	};
73
74	smmu_pcie: iommu@4f400000 {
75		compatible = "arm,smmu-v3";
76		reg = <0 0x4f400000 0 0x40000>;
77		interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
78				<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
79				<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
80				<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
81		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
82		msi-parent = <&its2 0>;
83		#iommu-cells = <1>;
84		dma-coherent;
85	};
86
87	pcie_ctlr: pcie@28c0000000 {
88		compatible = "pci-host-ecam-generic";
89		device_type = "pci";
90		reg = <0x28 0xC0000000 0 0x10000000>;
91		bus-range = <0 255>;
92		linux,pci-domain = <0>;
93		#address-cells = <3>;
94		#size-cells = <2>;
95		dma-coherent;
96		ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>,
97		     <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>,
98			 <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>;
99		#interrupt-cells = <1>;
100		interrupt-map-mask = <0 0 0 7>;
101		interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
102			<0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
103			<0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
104			<0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
105		msi-map = <0 &its_pcie 0 0x10000>;
106		iommu-map = <0 &smmu_pcie 0 0x10000>;
107		status = "okay";
108	};
109
110	smmu_ccix: iommu@4f000000 {
111		compatible = "arm,smmu-v3";
112		reg = <0 0x4f000000 0 0x40000>;
113		interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
114				<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
115				<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
116				<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
117		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
118		msi-parent = <&its1 0>;
119		#iommu-cells = <1>;
120		dma-coherent;
121	};
122
123	ccix_pcie_ctlr: pcie@4fc0000000 {
124		compatible = "pci-host-ecam-generic";
125		device_type = "pci";
126		reg = <0x4F 0xC0000000 0 0x10000000>;
127		bus-range = <0 255>;
128		linux,pci-domain = <1>;
129		#address-cells = <3>;
130		#size-cells = <2>;
131		dma-coherent;
132		ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>,
133		     <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>,
134			 <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>;
135		#interrupt-cells = <1>;
136		interrupt-map-mask = <0 0 0 7>;
137		interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
138			<0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
139			<0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
140			<0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
141		msi-map = <0 &its_ccix 0 0x10000>;
142		iommu-map = <0 &smmu_ccix 0 0x10000>;
143		status = "okay";
144	};
145
146	smmu_dp: iommu@2ce00000 {
147		compatible = "arm,smmu-v3";
148		reg = <0 0x2ce00000 0 0x40000>;
149		interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
150				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
151				<GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
152		interrupt-names = "eventq", "gerror", "cmdq-sync";
153		#iommu-cells = <1>;
154	};
155
156	dp0: display@2cc00000 {
157		#address-cells = <1>;
158		#size-cells = <0>;
159		compatible = "arm,mali-d32", "arm,mali-d71";
160		reg = <0 0x2cc00000 0 0x20000>;
161		interrupts = <0 69 4>;
162		interrupt-names = "DPU";
163		clocks = <&dpu_aclk>;
164		clock-names = "aclk";
165		iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
166			<&smmu_dp 8>;
167
168		pl0: pipeline@0 {
169			reg = <0>;
170			clocks = <&scmi_clk 1>;
171			clock-names = "pxclk";
172			pl_id = <0>;
173			ports {
174				#address-cells = <1>;
175				#size-cells = <0>;
176				port@0 {
177					reg = <0>;
178					dp_pl0_out0: endpoint {
179						remote-endpoint = <&tda998x_0_input>;
180					};
181				};
182			};
183		};
184	};
185
186	i2c@1c0f0000 {
187		compatible = "cdns,i2c-r1p14";
188		reg = <0x0 0x1c0f0000 0x0 0x1000>;
189		#address-cells = <1>;
190		#size-cells = <0>;
191		clock-frequency = <100000>;
192		i2c-sda-hold-time-ns = <500>;
193		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
194		clocks = <&dpu_aclk>;
195
196		hdmi-transmitter@70 {
197			compatible = "nxp,tda998x";
198			reg = <0x70>;
199			video-ports = <0x234501>;
200			port {
201				tda998x_0_input: endpoint {
202					remote-endpoint = <&dp_pl0_out0>;
203				};
204			};
205		};
206	};
207
208	dpu_aclk: dpu_aclk {
209		/* 77.1 MHz derived from 24 MHz reference clock */
210		compatible = "fixed-clock";
211		#clock-cells = <0>;
212		clock-frequency = <350000000>;
213		clock-output-names = "aclk";
214	};
215
216	firmware {
217		scmi {
218			compatible = "arm,scmi";
219			mbox-names = "tx", "rx";
220			mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
221			shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
222			#address-cells = <1>;
223			#size-cells = <0>;
224			scmi_dvfs: protocol@13 {
225				reg = <0x13>;
226				#clock-cells = <1>;
227			};
228			scmi_clk: protocol@14 {
229				reg = <0x14>;
230				#clock-cells = <1>;
231			};
232		};
233	};
234};
235
236&gic {
237	reg = <0x0 0x30000000 0 0x10000>,	/* GICD */
238	      <0x0 0x300c0000 0 0x80000>;	/* GICR */
239	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
240
241	its1: msi-controller@30040000 {
242		compatible = "arm,gic-v3-its";
243		msi-controller;
244		#msi-cells = <1>;
245		reg = <0x0 0x30040000 0x0 0x20000>;
246	};
247
248	its2: msi-controller@30060000 {
249		compatible = "arm,gic-v3-its";
250		msi-controller;
251		#msi-cells = <1>;
252		reg = <0x0 0x30060000 0x0 0x20000>;
253	};
254
255	its_ccix: msi-controller@30080000 {
256		compatible = "arm,gic-v3-its";
257		msi-controller;
258		#msi-cells = <1>;
259		reg = <0x0 0x30080000 0x0 0x20000>;
260	};
261
262	its_pcie: msi-controller@300a0000 {
263		compatible = "arm,gic-v3-its";
264		msi-controller;
265		#msi-cells = <1>;
266		reg = <0x0 0x300a0000 0x0 0x20000>;
267	};
268};
269