1// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
2/*
3 * Copyright (c) 2019-2022, Arm Limited.
4 */
5
6#include "n1sdp-single-chip.dts"
7
8/ {
9	cpus {
10		cpu4@100000000 {
11			compatible = "arm,neoverse-n1";
12			reg = <0x1 0x0>;
13			device_type = "cpu";
14			enable-method = "psci";
15			numa-node-id = <1>;
16		};
17		cpu5@100000100 {
18			compatible = "arm,neoverse-n1";
19			reg = <0x1 0x00000100>;
20			device_type = "cpu";
21			enable-method = "psci";
22			numa-node-id = <1>;
23		};
24		cpu6@100010000 {
25			compatible = "arm,neoverse-n1";
26			reg = <0x1 0x00010000>;
27			device_type = "cpu";
28			enable-method = "psci";
29			numa-node-id = <1>;
30		};
31		cpu7@100010100 {
32			compatible = "arm,neoverse-n1";
33			reg = <0x1 0x00010100>;
34			device_type = "cpu";
35			enable-method = "psci";
36			numa-node-id = <1>;
37		};
38	};
39
40	/* Remote N1SDP board address is mapped at offset 4TB.
41	 * First DRAM Bank of remote N1SDP board is mapped at 4TB + 2GB.
42	 */
43	memory@40080000000 {
44		device_type = "memory";
45		reg = <0x00000400 0x80000000 0x0 0x80000000>,
46			<0x00000480 0x80000000 0x3 0x80000000>;
47		numa-node-id = <1>;
48	};
49
50	distance-map {
51		compatible = "numa-distance-map-v1";
52		distance-matrix =   <0 0 10>,
53				    <0 1 20>,
54				    <1 1 10>;
55	};
56
57	smmu_secondary_pcie: iommu@4004f400000 {
58		compatible = "arm,smmu-v3";
59		reg = <0x400 0x4f400000 0 0x40000>;
60		interrupts = <GIC_SPI 715 IRQ_TYPE_EDGE_RISING>,
61				<GIC_SPI 716 IRQ_TYPE_EDGE_RISING>,
62				<GIC_SPI 717 IRQ_TYPE_EDGE_RISING>;
63		interrupt-names = "eventq", "cmdq-sync", "gerror";
64		msi-parent = <&its2_secondary 0>;
65		#iommu-cells = <1>;
66		dma-coherent;
67	};
68
69	pcie_secondary_ctlr: pcie@40070000000 {
70		compatible = "arm,n1sdp-pcie";
71		device_type = "pci";
72		reg = <0x400 0x70000000 0 0x1200000>;
73		bus-range = <0 0xff>;
74		linux,pci-domain = <2>;
75		#address-cells = <3>;
76		#size-cells = <2>;
77		dma-coherent;
78		ranges = <0x01000000 0x00 0x00000000 0x400 0x75200000 0x00 0x00010000>,
79			 <0x02000000 0x00 0x71200000 0x400 0x71200000 0x00 0x04000000>,
80			 <0x42000000 0x09 0x00000000 0x409 0x00000000 0x20 0x00000000>;
81		#interrupt-cells = <1>;
82		interrupt-map-mask = <0 0 0 7>;
83		interrupt-map = <0 0 0 1 &gic 0 0 0 649 IRQ_TYPE_LEVEL_HIGH>,
84				<0 0 0 2 &gic 0 0 0 650 IRQ_TYPE_LEVEL_HIGH>,
85				<0 0 0 3 &gic 0 0 0 651 IRQ_TYPE_LEVEL_HIGH>,
86				<0 0 0 4 &gic 0 0 0 652 IRQ_TYPE_LEVEL_HIGH>;
87		msi-map = <0 &its_secondary_pcie 0 0x10000>;
88		iommu-map = <0 &smmu_secondary_pcie 0 0x10000>;
89		numa-node-id = <1>;
90		status = "okay";
91	};
92
93};
94
95&gic {
96	#redistributor-regions = <2>;
97	reg =   <0x0 0x30000000 0 0x10000>,	/* GICD */
98		<0x0 0x300c0000 0 0x80000>,	/* GICR */
99		<0x400 0x300c0000 0 0x80000>;	/* GICR */
100
101	its2_secondary: its@40030060000 {
102		compatible = "arm,gic-v3-its";
103		msi-controller;
104		#msi-cells = <1>;
105		reg = <0x400 0x30060000 0x0 0x20000>;
106	};
107
108	its_secondary_pcie: its@400300a0000 {
109		compatible = "arm,gic-v3-its";
110		msi-controller;
111		#msi-cells = <1>;
112		reg = <0x400 0x300a0000 0x0 0x20000>;
113	};
114};
115
116&pcie_ctlr {
117	numa-node-id = <0>;
118};
119
120&ccix_pcie_ctlr {
121	numa-node-id = <0>;
122};
123