1// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
2/*
3 * Copyright (c) 2019-2020, Arm Limited.
4 */
5
6/dts-v1/;
7
8#include "n1sdp.dtsi"
9
10/ {
11	model = "Arm Neoverse N1 System Development Platform";
12	compatible = "arm,neoverse-n1-sdp", "arm,neoverse-n1-soc";
13
14	aliases {
15		serial0 = &soc_uart0;
16	};
17
18	chosen {
19		stdout-path = "serial0:115200n8";
20	};
21
22	/* This configuration assumes that standard setup with two DIMM modules.
23	 * In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory.
24	 * This configuration assumes 16GB of total DRAM being populated.
25	 */
26	memory@80000000 {
27		device_type = "memory";
28		reg = <0x00000000 0x80000000 0x0 0x7f000000>,
29			<0x00000080 0x80000000 0x3 0x80000000>;
30		numa-node-id = <0>;
31	};
32
33	soc_refclk60mhz: refclk60mhz {
34		compatible = "fixed-clock";
35		#clock-cells = <0>;
36		clock-frequency = <60000000>;
37		clock-output-names = "iofpga_clk";
38	};
39
40	soc_hdlcdclk:  hdlcdclk {
41		compatible = "fixed-clock";
42		#clock-cells = <0>;
43		clock-frequency = <23750000>;
44		clock-output-names = "hdlcdclk";
45	};
46
47	hdlcd: hdlcd@1c050000 {
48		compatible = "arm,hdlcd";
49		reg = <0 0x1c050000 0 0x1000>;
50		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
51		clocks = <&soc_hdlcdclk>;
52		clock-names = "pxlclk";
53
54		port {
55			hdlcd0_output: endpoint {
56				remote-endpoint = <&tda998x_0_input>;
57			};
58		};
59	};
60
61	i2c@1c0f0000 {
62		compatible = "arm,versatile-i2c";
63		reg = <0x0 0x1c0f0000 0x0 0x1000>;
64		#address-cells = <1>;
65		#size-cells = <0>;
66		clock-frequency = <400000>;
67		i2c-sda-hold-time-ns = <500>;
68		clocks = <&soc_refclk60mhz>;
69
70		hdmi-transmitter@70 {
71			compatible = "nxp,tda998x";
72			reg = <0x70>;
73			port {
74				tda998x_0_input: endpoint {
75					remote-endpoint = <&hdlcd0_output>;
76				};
77			};
78		};
79	};
80};
81
82&pcie_ctlr {
83	status = "okay";
84};
85
86&ccix_pcie_ctlr {
87	status = "okay";
88};
89
90&soc_uart0 {
91	status = "okay";
92};
93