1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * ARM Ltd. Fast Models
4 *
5 * Copyright (c) 2012-2022 ARM Ltd.
6 *
7 * Versatile Express (VE) system model
8 * Motherboard component
9 *
10 * VEMotherBoard.lisa
11 */
12/ {
13	v2m_clk24mhz: clk24mhz {
14		compatible = "fixed-clock";
15		#clock-cells = <0>;
16		clock-frequency = <24000000>;
17		clock-output-names = "v2m:clk24mhz";
18	};
19
20	v2m_refclk1mhz: refclk1mhz {
21		compatible = "fixed-clock";
22		#clock-cells = <0>;
23		clock-frequency = <1000000>;
24		clock-output-names = "v2m:refclk1mhz";
25	};
26
27	v2m_refclk32khz: refclk32khz {
28		compatible = "fixed-clock";
29		#clock-cells = <0>;
30		clock-frequency = <32768>;
31		clock-output-names = "v2m:refclk32khz";
32	};
33
34	v2m_fixed_3v3: v2m-3v3 {
35		compatible = "regulator-fixed";
36		regulator-name = "3V3";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		regulator-always-on;
40	};
41
42	mcc {
43		compatible = "arm,vexpress,config-bus";
44		arm,vexpress,config-bridge = <&v2m_sysreg>;
45
46		v2m_oscclk1: oscclk1 {
47			/* CLCD clock */
48			compatible = "arm,vexpress-osc";
49			arm,vexpress-sysreg,func = <1 1>;
50			freq-range = <23750000 63500000>;
51			#clock-cells = <0>;
52			clock-output-names = "v2m:oscclk1";
53		};
54
55		reset {
56			compatible = "arm,vexpress-reset";
57			arm,vexpress-sysreg,func = <5 0>;
58		};
59
60		muxfpga {
61			compatible = "arm,vexpress-muxfpga";
62			arm,vexpress-sysreg,func = <7 0>;
63		};
64
65		shutdown {
66			compatible = "arm,vexpress-shutdown";
67			arm,vexpress-sysreg,func = <8 0>;
68		};
69
70		reboot {
71			compatible = "arm,vexpress-reboot";
72			arm,vexpress-sysreg,func = <9 0>;
73		};
74
75		dvimode {
76			compatible = "arm,vexpress-dvimode";
77			arm,vexpress-sysreg,func = <11 0>;
78		};
79	};
80
81	bus@8000000 {
82		compatible = "simple-bus";
83		#address-cells = <2>;
84		#size-cells = <1>;
85		ranges = <0 0x8000000 0 0x8000000 0x18000000>;
86
87		motherboard-bus@8000000 {
88			compatible = "arm,vexpress,v2m-p1", "simple-bus";
89			#address-cells = <2>; /* SMB chipselect number and offset */
90			#size-cells = <1>;
91			ranges = <0 0 0 0x08000000 0x04000000>,
92				 <1 0 0 0x14000000 0x04000000>,
93				 <2 0 0 0x18000000 0x04000000>,
94				 <3 0 0 0x1c000000 0x04000000>,
95				 <4 0 0 0x0c000000 0x04000000>,
96				 <5 0 0 0x10000000 0x04000000>;
97
98			flash@0 {
99				compatible = "arm,vexpress-flash", "cfi-flash";
100				reg = <0 0x00000000 0x04000000>,
101				      <4 0x00000000 0x04000000>;
102				bank-width = <4>;
103			};
104
105			ethernet@202000000 {
106				compatible = "smsc,lan91c111";
107				reg = <2 0x02000000 0x10000>;
108				interrupts = <15>;
109			};
110
111			iofpga-bus@300000000 {
112				compatible = "simple-bus";
113				#address-cells = <1>;
114				#size-cells = <1>;
115				ranges = <0 3 0 0x210000>;
116
117				v2m_sysreg: sysreg@10000 {
118					compatible = "arm,vexpress-sysreg";
119					reg = <0x010000 0x1000>;
120					gpio-controller;
121					#gpio-cells = <2>;
122				};
123
124				v2m_sysctl: sysctl@20000 {
125					compatible = "arm,sp810", "arm,primecell";
126					reg = <0x020000 0x1000>;
127					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
128					clock-names = "refclk", "timclk", "apb_pclk";
129					#clock-cells = <1>;
130					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
131					assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
132					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
133				};
134
135				aaci@40000 {
136					compatible = "arm,pl041", "arm,primecell";
137					reg = <0x040000 0x1000>;
138					interrupts = <11>;
139					clocks = <&v2m_clk24mhz>;
140					clock-names = "apb_pclk";
141				};
142
143				mmc@50000 {
144					compatible = "arm,pl180", "arm,primecell";
145					reg = <0x050000 0x1000>;
146					interrupts = <9>, <10>;
147					cd-gpios = <&v2m_sysreg 0 0>;
148					wp-gpios = <&v2m_sysreg 1 0>;
149					max-frequency = <12000000>;
150					vmmc-supply = <&v2m_fixed_3v3>;
151					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
152					clock-names = "mclk", "apb_pclk";
153				};
154
155				kmi@60000 {
156					compatible = "arm,pl050", "arm,primecell";
157					reg = <0x060000 0x1000>;
158					interrupts = <12>;
159					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
160					clock-names = "KMIREFCLK", "apb_pclk";
161				};
162
163				kmi@70000 {
164					compatible = "arm,pl050", "arm,primecell";
165					reg = <0x070000 0x1000>;
166					interrupts = <13>;
167					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
168					clock-names = "KMIREFCLK", "apb_pclk";
169				};
170
171				v2m_serial0: serial@90000 {
172					compatible = "arm,pl011", "arm,primecell";
173					reg = <0x090000 0x1000>;
174					interrupts = <5>;
175					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
176					clock-names = "uartclk", "apb_pclk";
177				};
178
179				v2m_serial1: serial@a0000 {
180					compatible = "arm,pl011", "arm,primecell";
181					reg = <0x0a0000 0x1000>;
182					interrupts = <6>;
183					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
184					clock-names = "uartclk", "apb_pclk";
185				};
186
187				v2m_serial2: serial@b0000 {
188					compatible = "arm,pl011", "arm,primecell";
189					reg = <0x0b0000 0x1000>;
190					interrupts = <7>;
191					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
192					clock-names = "uartclk", "apb_pclk";
193				};
194
195				v2m_serial3: serial@c0000 {
196					compatible = "arm,pl011", "arm,primecell";
197					reg = <0x0c0000 0x1000>;
198					interrupts = <8>;
199					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
200					clock-names = "uartclk", "apb_pclk";
201				};
202
203				watchdog@f0000 {
204					compatible = "arm,sp805", "arm,primecell";
205					reg = <0x0f0000 0x1000>;
206					interrupts = <0>;
207					clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
208					clock-names = "wdog_clk", "apb_pclk";
209				};
210
211				v2m_timer01: timer@110000 {
212					compatible = "arm,sp804", "arm,primecell";
213					reg = <0x110000 0x1000>;
214					interrupts = <2>;
215					clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
216					clock-names = "timclken1", "timclken2", "apb_pclk";
217				};
218
219				v2m_timer23: timer@120000 {
220					compatible = "arm,sp804", "arm,primecell";
221					reg = <0x120000 0x1000>;
222					interrupts = <3>;
223					clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
224					clock-names = "timclken1", "timclken2", "apb_pclk";
225				};
226
227				virtio@130000 {
228					compatible = "virtio,mmio";
229					reg = <0x130000 0x200>;
230					interrupts = <42>;
231				};
232
233				rtc@170000 {
234					compatible = "arm,pl031", "arm,primecell";
235					reg = <0x170000 0x1000>;
236					interrupts = <4>;
237					clocks = <&v2m_clk24mhz>;
238					clock-names = "apb_pclk";
239				};
240
241				clcd@1f0000 {
242					compatible = "arm,pl111", "arm,primecell";
243					reg = <0x1f0000 0x1000>;
244					interrupt-names = "combined";
245					interrupts = <14>;
246					clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
247					clock-names = "clcdclk", "apb_pclk";
248					memory-region = <&vram>;
249
250					port {
251						clcd_pads: endpoint {
252							remote-endpoint = <&panel_in>;
253							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
254						};
255					};
256				};
257			};
258		};
259	};
260};
261