1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
4 */
5
6#include <common/tbbr/tbbr_img_def.h>
7#include <dt-bindings/soc/stm32mp13-tzc400.h>
8
9#include <platform_def.h>
10
11#ifndef DDR_SIZE
12#error "DDR_SIZE is not defined"
13#endif
14
15#define DDR_NS_BASE	STM32MP_DDR_BASE
16#define DDR_SEC_SIZE	STM32MP_DDR_S_SIZE
17#define DDR_SEC_BASE	(STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE))
18#define DDR_NS_SIZE	(DDR_SEC_BASE - DDR_NS_BASE)
19
20/dts-v1/;
21
22/ {
23	dtb-registry {
24		compatible = "fconf,dyn_cfg-dtb_registry";
25
26		hw-config {
27			load-address = <0x0 STM32MP_HW_CONFIG_BASE>;
28			max-size = <STM32MP_HW_CONFIG_MAX_SIZE>;
29			id = <HW_CONFIG_ID>;
30		};
31
32		nt_fw {
33			load-address = <0x0 STM32MP_BL33_BASE>;
34			max-size = <STM32MP_BL33_MAX_SIZE>;
35			id = <BL33_IMAGE_ID>;
36		};
37
38		tos_fw {
39			load-address = <0x0 DDR_SEC_BASE>;
40			max-size = <DDR_SEC_SIZE>;
41			id = <BL32_IMAGE_ID>;
42		};
43	};
44
45	st-mem-firewall {
46		compatible = "st,mem-firewall";
47		memory-ranges = <
48			DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR
49			DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0>;
50	};
51};
52