1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) Arrow Electronics 2019 - All Rights Reserved
4 * Author: Botond Kardos <botond.kardos@arroweurope.com>
5 *
6 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
7 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
8 */
9
10/dts-v1/;
11
12#include "stm32mp157.dtsi"
13#include "stm32mp15-pinctrl.dtsi"
14#include "stm32mp15xxac-pinctrl.dtsi"
15#include <dt-bindings/clock/stm32mp1-clksrc.h>
16#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
17
18/ {
19	model = "Arrow Electronics STM32MP157A Avenger96 board";
20	compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
21
22	aliases {
23		mmc0 = &sdmmc1;
24		serial0 = &uart4;
25		serial1 = &uart7;
26	};
27
28	chosen {
29		stdout-path = "serial0:115200n8";
30	};
31
32	memory@c0000000 {
33		device_type = "memory";
34		reg = <0xc0000000 0x40000000>;
35	};
36};
37
38&i2c4 {
39	pinctrl-names = "default";
40	pinctrl-0 = <&i2c4_pins_a>;
41	i2c-scl-rising-time-ns = <185>;
42	i2c-scl-falling-time-ns = <20>;
43	status = "okay";
44
45	pmic: stpmic@33 {
46		compatible = "st,stpmic1";
47		reg = <0x33>;
48		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
49		interrupt-controller;
50		#interrupt-cells = <2>;
51		status = "okay";
52
53		st,main-control-register = <0x04>;
54		st,vin-control-register = <0xc0>;
55		st,usb-control-register = <0x30>;
56
57		regulators {
58			compatible = "st,stpmic1-regulators";
59			ldo1-supply = <&v3v3>;
60			ldo2-supply = <&v3v3>;
61			ldo3-supply = <&vdd_ddr>;
62			ldo5-supply = <&v3v3>;
63			ldo6-supply = <&v3v3>;
64			pwr_sw1-supply = <&bst_out>;
65			pwr_sw2-supply = <&bst_out>;
66
67			vddcore: buck1 {
68				regulator-name = "vddcore";
69				regulator-min-microvolt = <1200000>;
70				regulator-max-microvolt = <1350000>;
71				regulator-always-on;
72				regulator-initial-mode = <0>;
73				regulator-over-current-protection;
74			};
75
76			vdd_ddr: buck2 {
77				regulator-name = "vdd_ddr";
78				regulator-min-microvolt = <1350000>;
79				regulator-max-microvolt = <1350000>;
80				regulator-always-on;
81				regulator-initial-mode = <0>;
82				regulator-over-current-protection;
83			};
84
85			vdd: buck3 {
86				regulator-name = "vdd";
87				regulator-min-microvolt = <3300000>;
88				regulator-max-microvolt = <3300000>;
89				regulator-always-on;
90				st,mask-reset;
91				regulator-initial-mode = <0>;
92				regulator-over-current-protection;
93			};
94
95			v3v3: buck4 {
96				regulator-name = "v3v3";
97				regulator-min-microvolt = <3300000>;
98				regulator-max-microvolt = <3300000>;
99				regulator-always-on;
100				regulator-over-current-protection;
101				regulator-initial-mode = <0>;
102			};
103
104			vdda: ldo1 {
105				regulator-name = "vdda";
106				regulator-min-microvolt = <2900000>;
107				regulator-max-microvolt = <2900000>;
108			};
109
110			v2v8: ldo2 {
111				regulator-name = "v2v8";
112				regulator-min-microvolt = <2800000>;
113				regulator-max-microvolt = <2800000>;
114			};
115
116			vtt_ddr: ldo3 {
117				regulator-name = "vtt_ddr";
118				regulator-always-on;
119				regulator-over-current-protection;
120				st,regulator-sink-source;
121			};
122
123			vdd_usb: ldo4 {
124				regulator-name = "vdd_usb";
125				regulator-min-microvolt = <3300000>;
126				regulator-max-microvolt = <3300000>;
127			};
128
129			vdd_sd: ldo5 {
130				regulator-name = "vdd_sd";
131				regulator-min-microvolt = <2900000>;
132				regulator-max-microvolt = <2900000>;
133				regulator-boot-on;
134			};
135
136			v1v8: ldo6 {
137				regulator-name = "v1v8";
138				regulator-min-microvolt = <1800000>;
139				regulator-max-microvolt = <1800000>;
140			};
141
142			vref_ddr: vref_ddr {
143				regulator-name = "vref_ddr";
144				regulator-always-on;
145			};
146
147			bst_out: boost {
148				regulator-name = "bst_out";
149			};
150
151			vbus_otg: pwr_sw1 {
152				regulator-name = "vbus_otg";
153			};
154
155			vbus_sw: pwr_sw2 {
156				regulator-name = "vbus_sw";
157				regulator-active-discharge = <1>;
158			};
159		};
160	};
161};
162
163&iwdg2 {
164	timeout-sec = <32>;
165	status = "okay";
166};
167
168&pwr_regulators {
169	vdd-supply = <&vdd>;
170	vdd_3v3_usbfs-supply = <&vdd_usb>;
171};
172
173&rcc {
174	st,clksrc = <
175		CLK_MPU_PLL1P
176		CLK_AXI_PLL2P
177		CLK_MCU_PLL3P
178		CLK_PLL12_HSE
179		CLK_PLL3_HSE
180		CLK_PLL4_HSE
181		CLK_RTC_LSE
182		CLK_MCO1_DISABLED
183		CLK_MCO2_DISABLED
184	>;
185
186	st,clkdiv = <
187		1 /*MPU*/
188		0 /*AXI*/
189		0 /*MCU*/
190		1 /*APB1*/
191		1 /*APB2*/
192		1 /*APB3*/
193		1 /*APB4*/
194		2 /*APB5*/
195		23 /*RTC*/
196		0 /*MCO1*/
197		0 /*MCO2*/
198	>;
199
200	st,pkcs = <
201		CLK_CKPER_HSE
202		CLK_FMC_ACLK
203		CLK_QSPI_ACLK
204		CLK_ETH_DISABLED
205		CLK_SDMMC12_PLL4P
206		CLK_DSI_DSIPLL
207		CLK_STGEN_HSE
208		CLK_USBPHY_HSE
209		CLK_SPI2S1_PLL3Q
210		CLK_SPI2S23_PLL3Q
211		CLK_SPI45_HSI
212		CLK_SPI6_HSI
213		CLK_I2C46_HSI
214		CLK_SDMMC3_PLL4P
215		CLK_USBO_USBPHY
216		CLK_ADC_CKPER
217		CLK_CEC_LSE
218		CLK_I2C12_HSI
219		CLK_I2C35_HSI
220		CLK_UART1_HSI
221		CLK_UART24_HSI
222		CLK_UART35_HSI
223		CLK_UART6_HSI
224		CLK_UART78_HSI
225		CLK_SPDIF_PLL4P
226		CLK_FDCAN_PLL4R
227		CLK_SAI1_PLL3Q
228		CLK_SAI2_PLL3Q
229		CLK_SAI3_PLL3Q
230		CLK_SAI4_PLL3Q
231		CLK_RNG1_LSI
232		CLK_RNG2_LSI
233		CLK_LPTIM1_PCLK1
234		CLK_LPTIM23_PCLK3
235		CLK_LPTIM45_LSE
236	>;
237
238	/* VCO = 1300.0 MHz => P = 650 (CPU) */
239	pll1: st,pll@0 {
240		compatible = "st,stm32mp1-pll";
241		reg = <0>;
242		cfg = <2 80 0 0 0 PQR(1,0,0)>;
243		frac = <0x800>;
244	};
245
246	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
247	pll2: st,pll@1 {
248		compatible = "st,stm32mp1-pll";
249		reg = <1>;
250		cfg = <2 65 1 0 0 PQR(1,1,1)>;
251		frac = <0x1400>;
252	};
253
254	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
255	pll3: st,pll@2 {
256		compatible = "st,stm32mp1-pll";
257		reg = <2>;
258		cfg = <1 33 1 16 36 PQR(1,1,1)>;
259		frac = <0x1a04>;
260	};
261
262	/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
263	pll4: st,pll@3 {
264		compatible = "st,stm32mp1-pll";
265		reg = <3>;
266		cfg = <1 39 3 11 4 PQR(1,1,1)>;
267	};
268};
269
270&rng1 {
271	status = "okay";
272};
273
274&rtc {
275	status = "okay";
276};
277
278&sdmmc1 {
279	pinctrl-names = "default";
280	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
281	st,sig-dir;
282	st,neg-edge;
283	st,use-ckin;
284	bus-width = <4>;
285	vmmc-supply = <&vdd_sd>;
286	status = "okay";
287};
288
289&uart4 {
290	/* On Low speed expansion header */
291	label = "LS-UART1";
292	pinctrl-names = "default";
293	pinctrl-0 = <&uart4_pins_b>;
294	status = "okay";
295};
296
297&uart7 {
298	/* On Low speed expansion header */
299	label = "LS-UART0";
300	pinctrl-names = "default";
301	pinctrl-0 = <&uart7_pins_a>;
302	status = "okay";
303};
304