1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6/dts-v1/;
7
8#include "stm32mp157.dtsi"
9#include "stm32mp15xc.dtsi"
10#include "stm32mp15-pinctrl.dtsi"
11#include "stm32mp15xxaa-pinctrl.dtsi"
12#include <dt-bindings/clock/stm32mp1-clksrc.h>
13#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
14
15/ {
16	model = "STMicroelectronics STM32MP157C eval daughter";
17	compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	memory@c0000000 {
24		device_type = "memory";
25		reg = <0xC0000000 0x40000000>;
26	};
27
28	aliases {
29		serial0 = &uart4;
30	};
31};
32
33&bsec {
34	board_id: board_id@ec {
35		reg = <0xec 0x4>;
36		st,non-secure-otp;
37	};
38};
39
40&clk_hse {
41	st,digbypass;
42};
43
44&cpu0 {
45	cpu-supply = <&vddcore>;
46};
47
48&cpu1 {
49	cpu-supply = <&vddcore>;
50};
51
52&cryp1 {
53	status = "okay";
54};
55
56&hash1 {
57	status = "okay";
58};
59
60&i2c4 {
61	pinctrl-names = "default";
62	pinctrl-0 = <&i2c4_pins_a>;
63	i2c-scl-rising-time-ns = <185>;
64	i2c-scl-falling-time-ns = <20>;
65	clock-frequency = <400000>;
66	status = "okay";
67
68	pmic: stpmic@33 {
69		compatible = "st,stpmic1";
70		reg = <0x33>;
71		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
72		interrupt-controller;
73		#interrupt-cells = <2>;
74		status = "okay";
75
76		regulators {
77			compatible = "st,stpmic1-regulators";
78			ldo1-supply = <&v3v3>;
79			ldo2-supply = <&v3v3>;
80			ldo3-supply = <&vdd_ddr>;
81			ldo5-supply = <&v3v3>;
82			ldo6-supply = <&v3v3>;
83			pwr_sw1-supply = <&bst_out>;
84			pwr_sw2-supply = <&bst_out>;
85
86			vddcore: buck1 {
87				regulator-name = "vddcore";
88				regulator-min-microvolt = <1200000>;
89				regulator-max-microvolt = <1350000>;
90				regulator-always-on;
91				regulator-initial-mode = <0>;
92				regulator-over-current-protection;
93			};
94
95			vdd_ddr: buck2 {
96				regulator-name = "vdd_ddr";
97				regulator-min-microvolt = <1350000>;
98				regulator-max-microvolt = <1350000>;
99				regulator-always-on;
100				regulator-initial-mode = <0>;
101				regulator-over-current-protection;
102			};
103
104			vdd: buck3 {
105				regulator-name = "vdd";
106				regulator-min-microvolt = <3300000>;
107				regulator-max-microvolt = <3300000>;
108				regulator-always-on;
109				st,mask-reset;
110				regulator-initial-mode = <0>;
111				regulator-over-current-protection;
112			};
113
114			v3v3: buck4 {
115				regulator-name = "v3v3";
116				regulator-min-microvolt = <3300000>;
117				regulator-max-microvolt = <3300000>;
118				regulator-always-on;
119				regulator-over-current-protection;
120				regulator-initial-mode = <0>;
121			};
122
123			vdda: ldo1 {
124				regulator-name = "vdda";
125				regulator-min-microvolt = <2900000>;
126				regulator-max-microvolt = <2900000>;
127			};
128
129			v2v8: ldo2 {
130				regulator-name = "v2v8";
131				regulator-min-microvolt = <2800000>;
132				regulator-max-microvolt = <2800000>;
133			};
134
135			vtt_ddr: ldo3 {
136				regulator-name = "vtt_ddr";
137				regulator-always-on;
138				regulator-over-current-protection;
139				st,regulator-sink-source;
140			};
141
142			vdd_usb: ldo4 {
143				regulator-name = "vdd_usb";
144				regulator-min-microvolt = <3300000>;
145				regulator-max-microvolt = <3300000>;
146			};
147
148			vdd_sd: ldo5 {
149				regulator-name = "vdd_sd";
150				regulator-min-microvolt = <2900000>;
151				regulator-max-microvolt = <2900000>;
152				regulator-boot-on;
153			};
154
155			v1v8: ldo6 {
156				regulator-name = "v1v8";
157				regulator-min-microvolt = <1800000>;
158				regulator-max-microvolt = <1800000>;
159			};
160
161			vref_ddr: vref_ddr {
162				regulator-name = "vref_ddr";
163				regulator-always-on;
164			};
165
166			bst_out: boost {
167				regulator-name = "bst_out";
168			};
169
170			vbus_otg: pwr_sw1 {
171				regulator-name = "vbus_otg";
172			 };
173
174			 vbus_sw: pwr_sw2 {
175				regulator-name = "vbus_sw";
176				regulator-active-discharge = <1>;
177			 };
178		};
179
180		onkey {
181			compatible = "st,stpmic1-onkey";
182			power-off-time-sec = <10>;
183			status = "okay";
184		};
185
186		watchdog {
187			compatible = "st,stpmic1-wdt";
188			status = "disabled";
189		};
190	};
191};
192
193&iwdg2 {
194	timeout-sec = <32>;
195	status = "okay";
196};
197
198&pwr_regulators {
199	vdd-supply = <&vdd>;
200	vdd_3v3_usbfs-supply = <&vdd_usb>;
201};
202
203&rcc {
204	st,clksrc = <
205		CLK_MPU_PLL1P
206		CLK_AXI_PLL2P
207		CLK_MCU_PLL3P
208		CLK_PLL12_HSE
209		CLK_PLL3_HSE
210		CLK_PLL4_HSE
211		CLK_RTC_LSE
212		CLK_MCO1_DISABLED
213		CLK_MCO2_DISABLED
214	>;
215
216	st,clkdiv = <
217		1 /*MPU*/
218		0 /*AXI*/
219		0 /*MCU*/
220		1 /*APB1*/
221		1 /*APB2*/
222		1 /*APB3*/
223		1 /*APB4*/
224		2 /*APB5*/
225		23 /*RTC*/
226		0 /*MCO1*/
227		0 /*MCO2*/
228	>;
229
230	st,pkcs = <
231		CLK_CKPER_HSE
232		CLK_FMC_ACLK
233		CLK_QSPI_ACLK
234		CLK_ETH_PLL4P
235		CLK_SDMMC12_PLL4P
236		CLK_DSI_DSIPLL
237		CLK_STGEN_HSE
238		CLK_USBPHY_HSE
239		CLK_SPI2S1_PLL3Q
240		CLK_SPI2S23_PLL3Q
241		CLK_SPI45_HSI
242		CLK_SPI6_HSI
243		CLK_I2C46_HSI
244		CLK_SDMMC3_PLL4P
245		CLK_USBO_USBPHY
246		CLK_ADC_CKPER
247		CLK_CEC_LSE
248		CLK_I2C12_HSI
249		CLK_I2C35_HSI
250		CLK_UART1_HSI
251		CLK_UART24_HSI
252		CLK_UART35_HSI
253		CLK_UART6_HSI
254		CLK_UART78_HSI
255		CLK_SPDIF_PLL4P
256		CLK_FDCAN_PLL4R
257		CLK_SAI1_PLL3Q
258		CLK_SAI2_PLL3Q
259		CLK_SAI3_PLL3Q
260		CLK_SAI4_PLL3Q
261		CLK_RNG1_LSI
262		CLK_RNG2_LSI
263		CLK_LPTIM1_PCLK1
264		CLK_LPTIM23_PCLK3
265		CLK_LPTIM45_LSE
266	>;
267
268	/* VCO = 1300.0 MHz => P = 650 (CPU) */
269	pll1: st,pll@0 {
270		compatible = "st,stm32mp1-pll";
271		reg = <0>;
272		cfg = <2 80 0 0 0 PQR(1,0,0)>;
273		frac = <0x800>;
274	};
275
276	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
277	pll2: st,pll@1 {
278		compatible = "st,stm32mp1-pll";
279		reg = <1>;
280		cfg = <2 65 1 0 0 PQR(1,1,1)>;
281		frac = <0x1400>;
282	};
283
284	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
285	pll3: st,pll@2 {
286		compatible = "st,stm32mp1-pll";
287		reg = <2>;
288		cfg = <1 33 1 16 36 PQR(1,1,1)>;
289		frac = <0x1a04>;
290	};
291
292	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
293	pll4: st,pll@3 {
294		compatible = "st,stm32mp1-pll";
295		reg = <3>;
296		cfg = <3 98 5 7 7 PQR(1,1,1)>;
297	};
298};
299
300&rng1 {
301	status = "okay";
302};
303
304&rtc {
305	status = "okay";
306};
307
308&sdmmc1 {
309	pinctrl-names = "default";
310	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
311	disable-wp;
312	st,sig-dir;
313	st,neg-edge;
314	st,use-ckin;
315	bus-width = <4>;
316	vmmc-supply = <&vdd_sd>;
317	sd-uhs-sdr12;
318	sd-uhs-sdr25;
319	sd-uhs-sdr50;
320	sd-uhs-ddr50;
321	status = "okay";
322};
323
324&sdmmc2 {
325	pinctrl-names = "default";
326	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
327	non-removable;
328	no-sd;
329	no-sdio;
330	st,neg-edge;
331	bus-width = <8>;
332	vmmc-supply = <&v3v3>;
333	vqmmc-supply = <&vdd>;
334	mmc-ddr-3_3v;
335	status = "okay";
336};
337
338&uart4 {
339	pinctrl-names = "default";
340	pinctrl-0 = <&uart4_pins_a>;
341	status = "okay";
342};
343