1 /*
2  * Copyright 2018-2021 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #if !defined(PLAT_TZC380_H) && defined(IMAGE_BL2)
8 #define PLAT_TZC380_H
9 
10 #include <tzc380.h>
11 
12 /* Number of DRAM regions to be configured
13  * for the platform can be over-written.
14  *
15  * Array tzc400_reg_list too, needs be over-written
16  * if there is any changes to default DRAM region
17  * configuration.
18  */
19 #ifndef MAX_NUM_TZC_REGION
20 /* 3 regions:
21  *  Region 0(default),
22  *  Region 1 (DRAM0, Secure Memory),
23  *  Region 2 (DRAM0, Shared memory)
24  */
25 #define MAX_NUM_TZC_REGION	3
26 #define DEFAULT_TZASC_CONFIG	1
27 #endif
28 
29 struct tzc380_reg {
30 	unsigned int secure;
31 	unsigned int enabled;
32 	uint64_t addr;
33 	uint64_t size;
34 	unsigned int sub_mask;
35 };
36 
37 void mem_access_setup(uintptr_t base, uint32_t total_regions,
38 			struct tzc380_reg *tzc380_reg_list);
39 
40 int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
41 			     int dram_idx, int list_idx,
42 			     uint64_t dram_start_addr,
43 			     uint64_t dram_size,
44 			     uint32_t secure_dram_sz,
45 			     uint32_t shrd_dram_sz);
46 
47 #endif /* PLAT_TZC380_H */
48