1 /* 2 * Copyright (c) 2022, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A510_H 8 #define CORTEX_A510_H 9 10 #define CORTEX_A510_MIDR U(0x410FD460) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions 14 ******************************************************************************/ 15 #define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 16 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) 17 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) 18 #define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) 19 #define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) 20 #define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) 21 #define CORTEX_A510_CPUECTLR_EL1_ATOM U(38) 22 23 /******************************************************************************* 24 * CPU Power Control register specific definitions 25 ******************************************************************************/ 26 #define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7 27 #define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 28 29 /******************************************************************************* 30 * Complex auxiliary control register specific definitions 31 ******************************************************************************/ 32 #define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 33 34 /******************************************************************************* 35 * Auxiliary control register specific definitions 36 ******************************************************************************/ 37 #define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 38 #define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) 39 #define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) 40 41 #endif /* CORTEX_A510_H */