1 /* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A710_H 8 #define CORTEX_A710_H 9 10 #define CORTEX_A710_MIDR U(0x410FD470) 11 12 /* Cortex-A710 loop count for CVE-2022-23960 mitigation */ 13 #define CORTEX_A710_BHB_LOOP_COUNT U(32) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions 17 ******************************************************************************/ 18 #define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4 19 #define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 20 21 /******************************************************************************* 22 * CPU Power Control register specific definitions 23 ******************************************************************************/ 24 #define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7 25 #define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 26 27 /******************************************************************************* 28 * CPU Auxiliary Control register specific definitions. 29 ******************************************************************************/ 30 #define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0 31 #define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 32 #define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 33 34 /******************************************************************************* 35 * CPU Auxiliary Control register 2 specific definitions. 36 ******************************************************************************/ 37 #define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1 38 #define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 39 #define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) 40 41 /******************************************************************************* 42 * CPU Auxiliary Control register 5 specific definitions. 43 ******************************************************************************/ 44 #define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0 45 #define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) 46 #define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 47 #define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 48 49 /******************************************************************************* 50 * CPU Auxiliary Control register specific definitions. 51 ******************************************************************************/ 52 #define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5 53 #define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 54 #define CPUECTLR2_EL1_PF_MODE_LSB U(11) 55 #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 56 57 /******************************************************************************* 58 * CPU Selected Instruction Private register specific definitions. 59 ******************************************************************************/ 60 #define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0 61 #define CORTEX_A710_CPUPCR_EL3 S3_6_C15_C8_1 62 #define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2 63 #define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3 64 65 #endif /* CORTEX_A710_H */ 66