1 /* 2 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A76_H 8 #define CORTEX_A76_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A76 MIDR for revision 0 */ 13 #define CORTEX_A76_MIDR U(0x410fd0b0) 14 15 /* Cortex-A76 loop count for CVE-2022-23960 mitigation */ 16 #define CORTEX_A76_BHB_LOOP_COUNT U(24) 17 18 /******************************************************************************* 19 * CPU Extended Control register specific definitions. 20 ******************************************************************************/ 21 #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22 #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 23 24 #define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) 25 #define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51) 26 27 /******************************************************************************* 28 * CPU Auxiliary Control register specific definitions. 29 ******************************************************************************/ 30 #define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 31 32 #define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) 33 34 #define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 35 36 #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 37 38 #define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 39 40 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) 41 42 #define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 43 44 #define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 45 46 47 /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ 48 #define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) 49 50 #endif /* CORTEX_A76_H */ 51