1 /*
2  * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_A76AE_H
8 #define CORTEX_A76AE_H
9 
10 #include <lib/utils_def.h>
11 
12 /* Cortex-A76AE MIDR for revision 0 */
13 #define CORTEX_A76AE_MIDR		U(0x410FD0E0)
14 
15 /* Cortex-A76 loop count for CVE-2022-23960 mitigation */
16 #define CORTEX_A76AE_BHB_LOOP_COUNT	U(24)
17 
18 /*******************************************************************************
19  * CPU Extended Control register specific definitions.
20  ******************************************************************************/
21 #define CORTEX_A76AE_CPUPWRCTLR_EL1	S3_0_C15_C2_7
22 
23 /* Definitions of register field mask in CORTEX_A76AE_CPUPWRCTLR_EL1 */
24 #define CORTEX_A76AE_CORE_PWRDN_EN_MASK	U(0x1)
25 
26 #define CORTEX_A76AE_CPUECTLR_EL1	S3_0_C15_C1_4
27 
28 #endif /* CORTEX_A76AE_H */
29