1 /* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A77_H 8 #define CORTEX_A77_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A77 MIDR */ 13 #define CORTEX_A77_MIDR U(0x410FD0D0) 14 15 /* Cortex-A77 loop count for CVE-2022-23960 mitigation */ 16 #define CORTEX_A77_BHB_LOOP_COUNT U(24) 17 18 /******************************************************************************* 19 * CPU Extended Control register specific definitions. 20 ******************************************************************************/ 21 #define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 22 #define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) 23 #define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) 24 25 /******************************************************************************* 26 * CPU Power Control register specific definitions. 27 ******************************************************************************/ 28 #define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29 #define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) 30 31 /******************************************************************************* 32 * CPU Auxiliary Control register specific definitions. 33 ******************************************************************************/ 34 #define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1 35 #define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 36 #define CORTEX_A77_ACTLR2_EL1_BIT_0 ULL(1) 37 38 #define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 39 #define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 40 #define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2 41 #define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3 42 #define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4 43 #define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5 44 45 #endif /* CORTEX_A77_H */ 46