1 /* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A78C_H 8 #define CORTEX_A78C_H 9 10 11 #define CORTEX_A78C_MIDR U(0x410FD4B1) 12 13 /* Cortex-A76 loop count for CVE-2022-23960 mitigation */ 14 #define CORTEX_A78C_BHB_LOOP_COUNT U(32) 15 16 /******************************************************************************* 17 * CPU Auxiliary Control register 2 specific definitions. 18 * ****************************************************************************/ 19 #define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1 20 #define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 21 #define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 22 23 /******************************************************************************* 24 * CPU Extended Control register specific definitions. 25 ******************************************************************************/ 26 #define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4 27 #define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6) 28 #define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7) 29 30 /******************************************************************************* 31 * CPU Power Control register specific definitions 32 ******************************************************************************/ 33 #define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7 34 #define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 35 36 /******************************************************************************* 37 * CPU Implementation Specific Selected Instruction registers 38 ******************************************************************************/ 39 #define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 40 #define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1 41 #define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2 42 #define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3 43 44 #endif /* CORTEX_A78C_H */ 45