1 /*
2  * Copyright (c) 2022, Google LLC. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_X1_H
8 #define CORTEX_X1_H
9 
10 /* Cortex-X1 MIDR for r1p0 */
11 #define CORTEX_X1_MIDR			U(0x411fd440)
12 
13 /* Cortex-X1 loop count for CVE-2022-23960 mitigation */
14 #define CORTEX_X1_BHB_LOOP_COUNT	U(32)
15 
16 /*******************************************************************************
17  * CPU Extended Control register specific definitions.
18  ******************************************************************************/
19 #define CORTEX_X1_CPUECTLR_EL1		S3_0_C15_C1_4
20 
21 /*******************************************************************************
22  * CPU Auxiliary Control register specific definitions.
23  ******************************************************************************/
24 #define CORTEX_X1_ACTLR2_EL1		S3_0_C15_C1_1
25 
26 /*******************************************************************************
27  * CPU Power Control register specific definitions
28  ******************************************************************************/
29 #define CORTEX_X1_CPUPWRCTLR_EL1	S3_0_C15_C2_7
30 #define CORTEX_X1_CORE_PWRDN_EN_MASK	U(0x1)
31 
32 #endif /* CORTEX_X1_H */
33