1 /* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_X2_H 8 #define CORTEX_X2_H 9 10 #define CORTEX_X2_MIDR U(0x410FD480) 11 12 /* Cortex-X2 loop count for CVE-2022-23960 mitigation */ 13 #define CORTEX_X2_BHB_LOOP_COUNT U(32) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions 17 ******************************************************************************/ 18 #define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 19 #define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 20 21 /******************************************************************************* 22 * CPU Extended Control register 2 specific definitions 23 ******************************************************************************/ 24 #define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5 25 26 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11) 27 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 28 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) 29 30 /******************************************************************************* 31 * CPU Power Control register specific definitions 32 ******************************************************************************/ 33 #define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 34 #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 35 36 /******************************************************************************* 37 * CPU Auxiliary Control Register definitions 38 ******************************************************************************/ 39 #define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0 40 #define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 41 42 /******************************************************************************* 43 * CPU Auxiliary Control Register 2 definitions 44 ******************************************************************************/ 45 #define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1 46 #define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 47 48 /******************************************************************************* 49 * CPU Auxiliary Control Register 5 definitions 50 ******************************************************************************/ 51 #define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 52 #define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 53 54 /******************************************************************************* 55 * CPU Implementation Specific Selected Instruction registers 56 ******************************************************************************/ 57 #define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 58 #define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1 59 #define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2 60 #define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3 61 62 #endif /* CORTEX_X2_H */ 63