1 /*
2  * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_X3_H
8 #define CORTEX_X3_H
9 
10 #define CORTEX_X3_MIDR				U(0x410FD4E0)
11 
12 /* Cortex-X3 loop count for CVE-2022-23960 mitigation */
13 #define CORTEX_X3_BHB_LOOP_COUNT			U(132)
14 
15 /*******************************************************************************
16  * CPU Extended Control register specific definitions
17  ******************************************************************************/
18 #define CORTEX_X3_CPUECTLR_EL1			S3_0_C15_C1_4
19 
20 /*******************************************************************************
21  * CPU Power Control register specific definitions
22  ******************************************************************************/
23 #define CORTEX_X3_CPUPWRCTLR_EL1			S3_0_C15_C2_7
24 #define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	U(1)
25 
26 /*******************************************************************************
27  * CPU Auxiliary Control register 2 specific definitions.
28  ******************************************************************************/
29 #define CORTEX_X3_CPUACTLR2_EL1			S3_0_C15_C1_1
30 #define CORTEX_X3_CPUACTLR2_EL1_BIT_36		(ULL(1) << 36)
31 
32 #endif /* CORTEX_X3_H */
33