1 /* 2 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NEOVERSE_N1_H 8 #define NEOVERSE_N1_H 9 10 #include <lib/utils_def.h> 11 12 /* Neoverse N1 MIDR for revision 0 */ 13 #define NEOVERSE_N1_MIDR U(0x410fd0c0) 14 15 /* Neoverse N1 loop count for CVE-2022-23960 mitigation */ 16 #define NEOVERSE_N1_BHB_LOOP_COUNT U(24) 17 18 /* Exception Syndrome register EC code for IC Trap */ 19 #define NEOVERSE_N1_EC_IC_TRAP U(0x1f) 20 21 /******************************************************************************* 22 * CPU Power Control register specific definitions. 23 ******************************************************************************/ 24 #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 25 26 /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ 27 #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) 28 29 #define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) 30 31 #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) 32 #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) 33 34 /******************************************************************************* 35 * CPU Extended Control register specific definitions. 36 ******************************************************************************/ 37 #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 38 39 #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) 40 #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) 41 #define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 42 43 /******************************************************************************* 44 * CPU Auxiliary Control register specific definitions. 45 ******************************************************************************/ 46 #define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 47 48 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) 49 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 50 51 #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 52 53 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 54 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 55 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) 56 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) 57 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) 58 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) 59 60 #define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 61 62 #define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 63 64 /* Instruction patching registers */ 65 #define CPUPSELR_EL3 S3_6_C15_C8_0 66 #define CPUPCR_EL3 S3_6_C15_C8_1 67 #define CPUPOR_EL3 S3_6_C15_C8_2 68 #define CPUPMR_EL3 S3_6_C15_C8_3 69 70 #endif /* NEOVERSE_N1_H */ 71