1/*
2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <assert_macros.S>
10#include <cortex_a9.h>
11#include <cpu_macros.S>
12
13	.macro assert_cache_enabled
14#if ENABLE_ASSERTIONS
15		ldcopr	r0, SCTLR
16		tst	r0, #SCTLR_C_BIT
17		ASM_ASSERT(eq)
18#endif
19	.endm
20
21func cortex_a9_disable_smp
22	ldcopr	r0, ACTLR
23	bic	r0, #CORTEX_A9_ACTLR_SMP_BIT
24	stcopr	r0, ACTLR
25	isb
26	dsb	sy
27	bx	lr
28endfunc cortex_a9_disable_smp
29
30func cortex_a9_enable_smp
31	ldcopr	r0, ACTLR
32	orr	r0, #CORTEX_A9_ACTLR_SMP_BIT
33	stcopr	r0, ACTLR
34	isb
35	bx	lr
36endfunc cortex_a9_enable_smp
37
38func check_errata_a9_794073
39#if ERRATA_A9_794073
40	mov	r0, #ERRATA_APPLIES
41#else
42	mov	r0, #ERRATA_MISSING
43#endif
44	bx	lr
45endfunc check_errata_cve_2017_5715
46
47func check_errata_cve_2017_5715
48#if WORKAROUND_CVE_2017_5715
49	mov	r0, #ERRATA_APPLIES
50#else
51	mov	r0, #ERRATA_MISSING
52#endif
53	bx	lr
54endfunc check_errata_cve_2017_5715
55
56#if REPORT_ERRATA
57/*
58 * Errata printing function for Cortex A9. Must follow AAPCS.
59 */
60func cortex_a9_errata_report
61	push	{r12, lr}
62
63	bl	cpu_get_rev_var
64	mov	r4, r0
65
66	/*
67	 * Report all errata. The revision-variant information is passed to
68	 * checking functions of each errata.
69	 */
70	report_errata WORKAROUND_CVE_2017_5715, cortex_a9, cve_2017_5715
71	report_errata ERRATA_A9_794073, cortex_a9, a9_79407
72
73	pop	{r12, lr}
74	bx	lr
75endfunc cortex_a9_errata_report
76#endif
77
78func cortex_a9_reset_func
79#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
80	ldr	r0, =workaround_bpiall_runtime_exceptions
81	stcopr	r0, VBAR
82	stcopr	r0, MVBAR
83	/* isb will be applied in the course of the reset func */
84#endif
85	b	cortex_a9_enable_smp
86endfunc cortex_a9_reset_func
87
88func cortex_a9_core_pwr_dwn
89	push	{r12, lr}
90
91	assert_cache_enabled
92
93	/* Flush L1 cache */
94	mov	r0, #DC_OP_CISW
95	bl	dcsw_op_level1
96
97	/* Exit cluster coherency */
98	pop	{r12, lr}
99	b	cortex_a9_disable_smp
100endfunc cortex_a9_core_pwr_dwn
101
102func cortex_a9_cluster_pwr_dwn
103	push	{r12, lr}
104
105	assert_cache_enabled
106
107	/* Flush L1 caches */
108	mov	r0, #DC_OP_CISW
109	bl	dcsw_op_level1
110
111	bl	plat_disable_acp
112
113	/* Exit cluster coherency */
114	pop	{r12, lr}
115	b	cortex_a9_disable_smp
116endfunc cortex_a9_cluster_pwr_dwn
117
118declare_cpu_ops cortex_a9, CORTEX_A9_MIDR, \
119	cortex_a9_reset_func, \
120	cortex_a9_core_pwr_dwn, \
121	cortex_a9_cluster_pwr_dwn
122