1/* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* -------------------------------------------------- 30 * Errata Workaround for Cortex-A710 Erratum 1987031. 31 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still 32 * open. 33 * Inputs: 34 * x0: variant[4:7] and revision[0:3] of current cpu. 35 * Shall clobber: x0-x17 36 * -------------------------------------------------- 37 */ 38func errata_a710_1987031_wa 39 /* Check revision. */ 40 mov x17, x30 41 bl check_errata_1987031 42 cbz x0, 1f 43 44 /* Apply instruction patching sequence */ 45 ldr x0,=0x6 46 msr S3_6_c15_c8_0,x0 47 ldr x0,=0xF3A08002 48 msr S3_6_c15_c8_2,x0 49 ldr x0,=0xFFF0F7FE 50 msr S3_6_c15_c8_3,x0 51 ldr x0,=0x40000001003ff 52 msr S3_6_c15_c8_1,x0 53 ldr x0,=0x7 54 msr S3_6_c15_c8_0,x0 55 ldr x0,=0xBF200000 56 msr S3_6_c15_c8_2,x0 57 ldr x0,=0xFFEF0000 58 msr S3_6_c15_c8_3,x0 59 ldr x0,=0x40000001003f3 60 msr S3_6_c15_c8_1,x0 61 isb 621: 63 ret x17 64endfunc errata_a710_1987031_wa 65 66func check_errata_1987031 67 /* Applies to r0p0, r1p0 and r2p0 */ 68 mov x1, #0x20 69 b cpu_rev_var_ls 70endfunc check_errata_1987031 71 72/* -------------------------------------------------- 73 * Errata Workaround for Cortex-A710 Erratum 2081180. 74 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. 75 * It is still open. 76 * Inputs: 77 * x0: variant[4:7] and revision[0:3] of current cpu. 78 * Shall clobber: x0-x17 79 * -------------------------------------------------- 80 */ 81func errata_a710_2081180_wa 82 /* Check revision. */ 83 mov x17, x30 84 bl check_errata_2081180 85 cbz x0, 1f 86 87 /* Apply instruction patching sequence */ 88 ldr x0,=0x3 89 msr S3_6_c15_c8_0,x0 90 ldr x0,=0xF3A08002 91 msr S3_6_c15_c8_2,x0 92 ldr x0,=0xFFF0F7FE 93 msr S3_6_c15_c8_3,x0 94 ldr x0,=0x10002001003FF 95 msr S3_6_c15_c8_1,x0 96 ldr x0,=0x4 97 msr S3_6_c15_c8_0,x0 98 ldr x0,=0xBF200000 99 msr S3_6_c15_c8_2,x0 100 ldr x0,=0xFFEF0000 101 msr S3_6_c15_c8_3,x0 102 ldr x0,=0x10002001003F3 103 msr S3_6_c15_c8_1,x0 104 isb 1051: 106 ret x17 107endfunc errata_a710_2081180_wa 108 109func check_errata_2081180 110 /* Applies to r0p0, r1p0 and r2p0 */ 111 mov x1, #0x20 112 b cpu_rev_var_ls 113endfunc check_errata_2081180 114 115/* --------------------------------------------------------------------- 116 * Errata Workaround for Cortex-A710 Erratum 2055002. 117 * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open. 118 * Inputs: 119 * x0: variant[4:7] and revision[0:3] of current cpu. 120 * Shall clobber: x0-x17 121 * --------------------------------------------------------------------- 122 */ 123func errata_a710_2055002_wa 124 /* Compare x0 against revision r2p0 */ 125 mov x17, x30 126 bl check_errata_2055002 127 cbz x0, 1f 128 mrs x1, CORTEX_A710_CPUACTLR_EL1 129 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 130 msr CORTEX_A710_CPUACTLR_EL1, x1 1311: 132 ret x17 133endfunc errata_a710_2055002_wa 134 135func check_errata_2055002 136 /* Applies to r1p0, r2p0 */ 137 mov x1, #0x20 138 b cpu_rev_var_ls 139endfunc check_errata_2055002 140 141/* ------------------------------------------------------------- 142 * Errata Workaround for Cortex-A710 Erratum 2017096. 143 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710. 144 * Inputs: 145 * x0: variant[4:7] and revision[0:3] of current cpu. 146 * Shall clobber: x0-x17 147 * ------------------------------------------------------------- 148 */ 149func errata_a710_2017096_wa 150 /* Compare x0 against revision r0p0 to r2p0 */ 151 mov x17, x30 152 bl check_errata_2017096 153 cbz x0, 1f 154 mrs x1, CORTEX_A710_CPUECTLR_EL1 155 orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 156 msr CORTEX_A710_CPUECTLR_EL1, x1 157 1581: 159 ret x17 160endfunc errata_a710_2017096_wa 161 162func check_errata_2017096 163 /* Applies to r0p0, r1p0, r2p0 */ 164 mov x1, #0x20 165 b cpu_rev_var_ls 166endfunc check_errata_2017096 167 168 169/* --------------------------------------------------------------------- 170 * Errata Workaround for Cortex-A710 Erratum 2083908. 171 * This applies to revision r2p0 of Cortex-A710 and is still open. 172 * Inputs: 173 * x0: variant[4:7] and revision[0:3] of current cpu. 174 * Shall clobber: x0-x17 175 * --------------------------------------------------------------------- 176 */ 177func errata_a710_2083908_wa 178 /* Compare x0 against revision r2p0 */ 179 mov x17, x30 180 bl check_errata_2083908 181 cbz x0, 1f 182 mrs x1, CORTEX_A710_CPUACTLR5_EL1 183 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 184 msr CORTEX_A710_CPUACTLR5_EL1, x1 1851: 186 ret x17 187endfunc errata_a710_2083908_wa 188 189func check_errata_2083908 190 /* Applies to r2p0 */ 191 mov x1, #CPU_REV(2, 0) 192 mov x2, #CPU_REV(2, 0) 193 b cpu_rev_var_range 194endfunc check_errata_2083908 195 196/* --------------------------------------------------------------------- 197 * Errata Workaround for Cortex-A710 Erratum 2058056. 198 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still 199 * open. 200 * Inputs: 201 * x0: variant[4:7] and revision[0:3] of current cpu. 202 * Shall clobber: x0-x17 203 * --------------------------------------------------------------------- 204 */ 205func errata_a710_2058056_wa 206 /* Compare x0 against revision r2p0 */ 207 mov x17, x30 208 bl check_errata_2058056 209 cbz x0, 1f 210 mrs x1, CORTEX_A710_CPUECTLR2_EL1 211 mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV 212 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 213 msr CORTEX_A710_CPUECTLR2_EL1, x1 2141: 215 ret x17 216endfunc errata_a710_2058056_wa 217 218func check_errata_2058056 219 /* Applies to r0p0, r1p0 and r2p0 */ 220 mov x1, #0x20 221 b cpu_rev_var_ls 222endfunc check_errata_2058056 223 224/* -------------------------------------------------- 225 * Errata Workaround for Cortex-A710 Erratum 2267065. 226 * This applies to revisions r0p0, r1p0 and r2p0. 227 * It is fixed in r2p1. 228 * Inputs: 229 * x0: variant[4:7] and revision[0:3] of current cpu. 230 * Shall clobber: x0-x1, x17 231 * -------------------------------------------------- 232 */ 233func errata_a710_2267065_wa 234 /* Compare x0 against revision r2p0 */ 235 mov x17, x30 236 bl check_errata_2267065 237 cbz x0, 1f 238 239 /* Apply instruction patching sequence */ 240 mrs x1, CORTEX_A710_CPUACTLR_EL1 241 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 242 msr CORTEX_A710_CPUACTLR_EL1, x1 2431: 244 ret x17 245endfunc errata_a710_2267065_wa 246 247func check_errata_2267065 248 /* Applies to r0p0, r1p0 and r2p0 */ 249 mov x1, #0x20 250 b cpu_rev_var_ls 251endfunc check_errata_2267065 252 253/* --------------------------------------------------------------- 254 * Errata Workaround for Cortex-A710 Erratum 2136059. 255 * This applies to revision r0p0, r1p0 and r2p0. 256 * It is fixed in r2p1. 257 * Inputs: 258 * x0: variant[4:7] and revision[0:3] of current cpu. 259 * Shall clobber: x0-x17 260 * --------------------------------------------------------------- 261 */ 262func errata_a710_2136059_wa 263 /* Compare x0 against revision r2p0 */ 264 mov x17, x30 265 bl check_errata_2136059 266 cbz x0, 1f 267 268 /* Apply the workaround */ 269 mrs x1, CORTEX_A710_CPUACTLR5_EL1 270 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 271 msr CORTEX_A710_CPUACTLR5_EL1, x1 272 2731: 274 ret x17 275endfunc errata_a710_2136059_wa 276 277func check_errata_2136059 278 /* Applies to r0p0, r1p0 and r2p0 */ 279 mov x1, #0x20 280 b cpu_rev_var_ls 281endfunc check_errata_2136059 282 283/* ---------------------------------------------------------------- 284 * Errata workaround for Cortex-A710 Erratum 2147715. 285 * This applies to revision r2p0, and is fixed in r2p1. 286 * Inputs: 287 * x0: variant[4:7] and revision[0:3] of current cpu. 288 * Shall clobber: x0, x1, x17 289 * ---------------------------------------------------------------- 290 */ 291func errata_a710_2147715_wa 292 mov x17, x30 293 bl check_errata_2147715 294 cbz x0, 1f 295 296 /* Apply workaround; set CPUACTLR_EL1[22] 297 * to 1, which will cause the CFP instruction 298 * to invalidate all branch predictor resources 299 * regardless of context. 300 */ 301 mrs x1, CORTEX_A710_CPUACTLR_EL1 302 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 303 msr CORTEX_A710_CPUACTLR_EL1, x1 3041: 305 ret x17 306endfunc errata_a710_2147715_wa 307 308func check_errata_2147715 309 mov x1, #0x20 310 mov x2, #0x20 311 b cpu_rev_var_range 312endfunc check_errata_2147715 313 314/* --------------------------------------------------------------- 315 * Errata Workaround for Cortex-A710 Erratum 2216384. 316 * This applies to revision r0p0, r1p0 and r2p0. 317 * It is fixed in r2p1. 318 * Inputs: 319 * x0: variant[4:7] and revision[0:3] of current cpu. 320 * Shall clobber: x0-x17 321 * --------------------------------------------------------------- 322 */ 323func errata_a710_2216384_wa 324 /* Compare x0 against revision r2p0 */ 325 mov x17, x30 326 bl check_errata_2216384 327 cbz x0, 1f 328 329 /* Apply workaround: set CPUACTLR5_EL1[17] 330 * to 1 and the following instruction 331 * patching sequence. 332 */ 333 mrs x1, CORTEX_A710_CPUACTLR5_EL1 334 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 335 msr CORTEX_A710_CPUACTLR5_EL1, x1 336 337 ldr x0,=0x5 338 msr CORTEX_A710_CPUPSELR_EL3, x0 339 ldr x0,=0x10F600E000 340 msr CORTEX_A710_CPUPOR_EL3, x0 341 ldr x0,=0x10FF80E000 342 msr CORTEX_A710_CPUPMR_EL3, x0 343 ldr x0,=0x80000000003FF 344 msr CORTEX_A710_CPUPCR_EL3, x0 345 isb 3461: 347 ret x17 348endfunc errata_a710_2216384_wa 349 350func check_errata_2216384 351 /* Applies to r0p0, r1p0 and r2p0 */ 352 mov x1, #0x20 353 b cpu_rev_var_ls 354endfunc check_errata_2216384 355 356/* --------------------------------------------------------------- 357 * Errata Workaround for Cortex-A710 Erratum 2282622. 358 * This applies to revision r0p0, r1p0 and r2p0. 359 * It is fixed in r2p1. 360 * Inputs: 361 * x0: variant[4:7] and revision[0:3] of current cpu. 362 * Shall clobber: x0, x1, x17 363 * --------------------------------------------------------------- 364 */ 365func errata_a710_2282622_wa 366 /* Compare x0 against revision r2p0 */ 367 mov x17, x30 368 bl check_errata_2282622 369 cbz x0, 1f 370 371 /* Apply the workaround */ 372 mrs x1, CORTEX_A710_CPUACTLR2_EL1 373 orr x1, x1, BIT(0) 374 msr CORTEX_A710_CPUACTLR2_EL1, x1 375 3761: 377 ret x17 378endfunc errata_a710_2282622_wa 379 380func check_errata_2282622 381 /* Applies to r0p0, r1p0 and r2p0 */ 382 mov x1, #0x20 383 b cpu_rev_var_ls 384endfunc check_errata_2282622 385 386/* ------------------------------------------------------------------------ 387 * Errata Workaround for Cortex-A710 Erratum 2291219 on power down request. 388 * This applies to revision <= r2p0 and is fixed in r2p1. 389 * Inputs: 390 * x0: variant[4:7] and revision[0:3] of current cpu. 391 * Shall clobber: x0-x1, x17 392 * ------------------------------------------------------------------------ 393 */ 394func errata_a710_2291219_wa 395 /* Check revision. */ 396 mov x17, x30 397 bl check_errata_2291219 398 cbz x0, 1f 399 400 /* Set bit 36 in ACTLR2_EL1 */ 401 mrs x1, CORTEX_A710_CPUACTLR2_EL1 402 orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_36 403 msr CORTEX_A710_CPUACTLR2_EL1, x1 4041: 405 ret x17 406endfunc errata_a710_2291219_wa 407 408func check_errata_2291219 409 /* Applies to <= r2p0. */ 410 mov x1, #0x20 411 b cpu_rev_var_ls 412endfunc check_errata_2291219 413 414/* --------------------------------------------------------------- 415 * Errata Workaround for Cortex-A710 Erratum 2008768. 416 * This applies to revision r0p0, r1p0 and r2p0. 417 * It is fixed in r2p1. 418 * Inputs: 419 * x0: variant[4:7] and revision[0:3] of current cpu. 420 * Shall clobber: x0, x1, x2, x17 421 * --------------------------------------------------------------- 422 */ 423func errata_a710_2008768_wa 424 mov x17, x30 425 bl check_errata_2008768 426 cbz x0, 1f 427 428 /* Stash ERRSELR_EL1 in x2 */ 429 mrs x2, ERRSELR_EL1 430 431 /* Select error record 0 and clear ED bit */ 432 msr ERRSELR_EL1, xzr 433 mrs x1, ERXCTLR_EL1 434 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 435 msr ERXCTLR_EL1, x1 436 437 /* Select error record 1 and clear ED bit */ 438 mov x0, #1 439 msr ERRSELR_EL1, x0 440 mrs x1, ERXCTLR_EL1 441 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 442 msr ERXCTLR_EL1, x1 443 444 /* Restore ERRSELR_EL1 from x2 */ 445 msr ERRSELR_EL1, x2 446 4471: 448 ret x17 449endfunc errata_a710_2008768_wa 450 451func check_errata_2008768 452 /* Applies to r0p0, r1p0 and r2p0 */ 453 mov x1, #0x20 454 b cpu_rev_var_ls 455endfunc check_errata_2008768 456 457/* ------------------------------------------------------- 458 * Errata Workaround for Cortex-A710 Erratum 2371105. 459 * This applies to revisions <= r2p0 and is fixed in r2p1. 460 * x0: variant[4:7] and revision[0:3] of current cpu. 461 * Shall clobber: x0-x17 462 * ------------------------------------------------------- 463 */ 464func errata_a710_2371105_wa 465 /* Check workaround compatibility. */ 466 mov x17, x30 467 bl check_errata_2371105 468 cbz x0, 1f 469 470 /* Set bit 40 in CPUACTLR2_EL1 */ 471 mrs x1, CORTEX_A710_CPUACTLR2_EL1 472 orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_40 473 msr CORTEX_A710_CPUACTLR2_EL1, x1 474 isb 4751: 476 ret x17 477endfunc errata_a710_2371105_wa 478 479func check_errata_2371105 480 /* Applies to <= r2p0. */ 481 mov x1, #0x20 482 b cpu_rev_var_ls 483endfunc check_errata_2371105 484 485func check_errata_cve_2022_23960 486#if WORKAROUND_CVE_2022_23960 487 mov x0, #ERRATA_APPLIES 488#else 489 mov x0, #ERRATA_MISSING 490#endif 491 ret 492endfunc check_errata_cve_2022_23960 493 494 /* ---------------------------------------------------- 495 * HW will do the cache maintenance while powering down 496 * ---------------------------------------------------- 497 */ 498func cortex_a710_core_pwr_dwn 499 500#if ERRATA_A710_2008768 501 mov x4, x30 502 bl cpu_get_rev_var 503 bl errata_a710_2008768_wa 504 mov x30, x4 505#endif 506 507#if ERRATA_A710_2291219 508 mov x15, x30 509 bl cpu_get_rev_var 510 bl errata_a710_2291219_wa 511 mov x30, x15 512#endif /* ERRATA_A710_2291219 */ 513 514 /* --------------------------------------------------- 515 * Enable CPU power down bit in power control register 516 * --------------------------------------------------- 517 */ 518 mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 519 orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 520 msr CORTEX_A710_CPUPWRCTLR_EL1, x0 521 isb 522 ret 523endfunc cortex_a710_core_pwr_dwn 524 525#if REPORT_ERRATA 526 /* 527 * Errata printing function for Cortex-A710. Must follow AAPCS. 528 */ 529func cortex_a710_errata_report 530 stp x8, x30, [sp, #-16]! 531 532 bl cpu_get_rev_var 533 mov x8, x0 534 535 /* 536 * Report all errata. The revision-variant information is passed to 537 * checking functions of each errata. 538 */ 539 report_errata ERRATA_A710_1987031, cortex_a710, 1987031 540 report_errata ERRATA_A710_2081180, cortex_a710, 2081180 541 report_errata ERRATA_A710_2055002, cortex_a710, 2055002 542 report_errata ERRATA_A710_2017096, cortex_a710, 2017096 543 report_errata ERRATA_A710_2083908, cortex_a710, 2083908 544 report_errata ERRATA_A710_2058056, cortex_a710, 2058056 545 report_errata ERRATA_A710_2267065, cortex_a710, 2267065 546 report_errata ERRATA_A710_2136059, cortex_a710, 2136059 547 report_errata ERRATA_A710_2282622, cortex_a710, 2282622 548 report_errata ERRATA_A710_2008768, cortex_a710, 2008768 549 report_errata ERRATA_A710_2147715, cortex_a710, 2147715 550 report_errata ERRATA_A710_2216384, cortex_a710, 2216384 551 report_errata ERRATA_A710_2291219, cortex_a710, 2291219 552 report_errata ERRATA_A710_2371105, cortex_a710, 2371105 553 report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960 554 report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941 555 556 ldp x8, x30, [sp], #16 557 ret 558endfunc cortex_a710_errata_report 559#endif 560 561func cortex_a710_reset_func 562 mov x19, x30 563 564 /* Disable speculative loads */ 565 msr SSBS, xzr 566 567 bl cpu_get_rev_var 568 mov x18, x0 569 570#if ERRATA_DSU_2313941 571 bl errata_dsu_2313941_wa 572#endif 573 574#if ERRATA_A710_1987031 575 mov x0, x18 576 bl errata_a710_1987031_wa 577#endif 578 579#if ERRATA_A710_2081180 580 mov x0, x18 581 bl errata_a710_2081180_wa 582#endif 583 584#if ERRATA_A710_2055002 585 mov x0, x18 586 bl errata_a710_2055002_wa 587#endif 588 589#if ERRATA_A710_2017096 590 mov x0, x18 591 bl errata_a710_2017096_wa 592#endif 593 594#if ERRATA_A710_2083908 595 mov x0, x18 596 bl errata_a710_2083908_wa 597#endif 598 599#if ERRATA_A710_2058056 600 mov x0, x18 601 bl errata_a710_2058056_wa 602#endif 603 604#if ERRATA_A710_2267065 605 mov x0, x18 606 bl errata_a710_2267065_wa 607#endif 608 609#if ERRATA_A710_2136059 610 mov x0, x18 611 bl errata_a710_2136059_wa 612#endif 613 614#if ERRATA_A710_2147715 615 mov x0, x18 616 bl errata_a710_2147715_wa 617#endif 618 619#if ERRATA_A710_2216384 620 mov x0, x18 621 bl errata_a710_2216384_wa 622#endif /* ERRATA_A710_2216384 */ 623 624#if ERRATA_A710_2282622 625 mov x0, x18 626 bl errata_a710_2282622_wa 627#endif 628 629#if ERRATA_A710_2371105 630 mov x0, x18 631 bl errata_a710_2371105_wa 632#endif 633 634#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 635 /* 636 * The Cortex-A710 generic vectors are overridden to apply errata 637 * mitigation on exception entry from lower ELs. 638 */ 639 adr x0, wa_cve_vbar_cortex_a710 640 msr vbar_el3, x0 641#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 642 643 isb 644 ret x19 645endfunc cortex_a710_reset_func 646 647 /* --------------------------------------------- 648 * This function provides Cortex-A710 specific 649 * register information for crash reporting. 650 * It needs to return with x6 pointing to 651 * a list of register names in ascii and 652 * x8 - x15 having values of registers to be 653 * reported. 654 * --------------------------------------------- 655 */ 656.section .rodata.cortex_a710_regs, "aS" 657cortex_a710_regs: /* The ascii list of register names to be reported */ 658 .asciz "cpuectlr_el1", "" 659 660func cortex_a710_cpu_reg_dump 661 adr x6, cortex_a710_regs 662 mrs x8, CORTEX_A710_CPUECTLR_EL1 663 ret 664endfunc cortex_a710_cpu_reg_dump 665 666declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 667 cortex_a710_reset_func, \ 668 cortex_a710_core_pwr_dwn 669