1/*
2 * Copyright (c) 2022, Google LLC. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <asm_macros.S>
8#include <cortex_x1.h>
9#include <cpu_macros.S>
10#include "wa_cve_2022_23960_bhb_vector.S"
11
12/* Hardware handled coherency */
13#if HW_ASSISTED_COHERENCY == 0
14#error "Cortex-X1 must be compiled with HW_ASSISTED_COHERENCY enabled"
15#endif
16
17/* 64-bit only core */
18#if CTX_INCLUDE_AARCH32_REGS == 1
19#error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
20#endif
21
22#if WORKAROUND_CVE_2022_23960
23	wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1
24#endif /* WORKAROUND_CVE_2022_23960 */
25
26/* --------------------------------------------------
27 * Errata Workaround for X1 Erratum 1821534.
28 * This applies to revision r0p0 and r1p0 of X1.
29 * Inputs:
30 * x0: variant[4:7] and revision[0:3] of current cpu.
31 * Shall clobber: x0-x17
32 * --------------------------------------------------
33 */
34func errata_x1_1821534_wa
35	/* Compare x0 against revision r1p0 */
36	mov	x17, x30
37	bl	check_errata_1821534
38	cbz	x0, 1f
39	mrs	x1, CORTEX_X1_ACTLR2_EL1
40	orr	x1, x1, BIT(2)
41	msr	CORTEX_X1_ACTLR2_EL1, x1
42	isb
431:
44	ret	x17
45endfunc errata_x1_1821534_wa
46
47func check_errata_1821534
48	/* Applies to r0p0 and r1p0 */
49	mov	x1, #0x10
50	b	cpu_rev_var_ls
51endfunc check_errata_1821534
52
53/* --------------------------------------------------
54 * Errata Workaround for X1 Erratum 1688305.
55 * This applies to revision r0p0 and r1p0 of X1.
56 * Inputs:
57 * x0: variant[4:7] and revision[0:3] of current cpu.
58 * Shall clobber: x0-x17
59 * --------------------------------------------------
60 */
61func errata_x1_1688305_wa
62	/* Compare x0 against revision r1p0 */
63	mov	x17, x30
64	bl	check_errata_1688305
65	cbz	x0, 1f
66	mrs	x0, CORTEX_X1_ACTLR2_EL1
67	orr	x0, x0, BIT(1)
68	msr	CORTEX_X1_ACTLR2_EL1, x0
69	isb
70
711:
72	ret	x17
73endfunc errata_x1_1688305_wa
74
75func check_errata_1688305
76	/* Applies to r0p0 and r1p0 */
77	mov	x1, #0x10
78	b	cpu_rev_var_ls
79endfunc check_errata_1688305
80
81/* --------------------------------------------------
82 * Errata Workaround for X1 Erratum 1827429.
83 * This applies to revision r0p0 and r1p0 of X1.
84 * Inputs:
85 * x0: variant[4:7] and revision[0:3] of current cpu.
86 * Shall clobber: x0-x17
87 * --------------------------------------------------
88 */
89func errata_x1_1827429_wa
90	/* Compare x0 against revision r1p0 */
91	mov	x17, x30
92	bl	check_errata_1827429
93	cbz	x0, 1f
94	mrs	x0, CORTEX_X1_CPUECTLR_EL1
95	orr	x0, x0, BIT(53)
96	msr	CORTEX_X1_CPUECTLR_EL1, x0
97	isb
98
991:
100	ret	x17
101endfunc errata_x1_1827429_wa
102
103func check_errata_1827429
104	/* Applies to r0p0 and r1p0 */
105	mov	x1, #0x10
106	b	cpu_rev_var_ls
107endfunc check_errata_1827429
108
109func check_errata_cve_2022_23960
110#if WORKAROUND_CVE_2022_23960
111	mov	x0, #ERRATA_APPLIES
112#else
113	mov	x0, #ERRATA_MISSING
114#endif
115	ret
116endfunc check_errata_cve_2022_23960
117
118	/* -------------------------------------------------
119	 * The CPU Ops reset function for Cortex-X1.
120	 * Shall clobber: x0-x19
121	 * -------------------------------------------------
122	 */
123func cortex_x1_reset_func
124	mov	x19, x30
125	bl	cpu_get_rev_var
126	mov	x18, x0
127
128#if ERRATA_X1_1821534
129	mov	x0, x18
130	bl	errata_x1_1821534_wa
131#endif
132
133#if ERRATA_X1_1688305
134	mov	x0, x18
135	bl	errata_x1_1688305_wa
136#endif
137
138#if ERRATA_X1_1827429
139	mov	x0, x18
140	bl	errata_x1_1827429_wa
141#endif
142
143#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
144	/*
145	 * The Cortex-X1 generic vectors are overridden to apply errata
146	 * mitigation on exception entry from lower ELs.
147	 */
148	adr	x0, wa_cve_vbar_cortex_x1
149	msr	vbar_el3, x0
150#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
151
152	isb
153	ret	x19
154endfunc cortex_x1_reset_func
155
156	/* ---------------------------------------------
157	 * HW will do the cache maintenance while powering down
158	 * ---------------------------------------------
159	 */
160func cortex_x1_core_pwr_dwn
161	/* ---------------------------------------------
162	 * Enable CPU power down bit in power control register
163	 * ---------------------------------------------
164	 */
165	mrs	x0, CORTEX_X1_CPUPWRCTLR_EL1
166	orr	x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK
167	msr	CORTEX_X1_CPUPWRCTLR_EL1, x0
168	isb
169	ret
170endfunc cortex_x1_core_pwr_dwn
171
172#if REPORT_ERRATA
173/*
174 * Errata printing function for Cortex X1. Must follow AAPCS.
175 */
176func cortex_x1_errata_report
177	stp	x8, x30, [sp, #-16]!
178
179	bl	cpu_get_rev_var
180	mov	x8, x0
181
182	/*
183	 * Report all errata. The revision-variant information is passed to
184	 * checking functions of each errata.
185	 */
186	report_errata ERRATA_X1_1821534, cortex_x1, 1821534
187	report_errata ERRATA_X1_1688305, cortex_x1, 1688305
188	report_errata ERRATA_X1_1827429, cortex_x1, 1827429
189	report_errata WORKAROUND_CVE_2022_23960, cortex_x1, cve_2022_23960
190
191	ldp	x8, x30, [sp], #16
192	ret
193endfunc cortex_x1_errata_report
194#endif
195
196       /* ---------------------------------------------
197	* This function provides Cortex X1 specific
198	* register information for crash reporting.
199	* It needs to return with x6 pointing to
200	* a list of register names in ascii and
201	* x8 - x15 having values of registers to be
202	* reported.
203	* ---------------------------------------------
204	*/
205.section .rodata.cortex_x1_regs, "aS"
206cortex_x1_regs:  /* The ascii list of register names to be reported */
207	.asciz	"cpuectlr_el1", ""
208
209func cortex_x1_cpu_reg_dump
210	adr	x6, cortex_x1_regs
211	mrs	x8, CORTEX_X1_CPUECTLR_EL1
212	ret
213endfunc cortex_x1_cpu_reg_dump
214
215declare_cpu_ops cortex_x1, CORTEX_X1_MIDR, \
216	cortex_x1_reset_func, \
217	cortex_x1_core_pwr_dwn
218