1/*
2 * Copyright (c) 2022, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <neoverse_poseidon.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Neoverse Poseidon must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Neoverse Poseidon supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
25#if WORKAROUND_CVE_2022_23960
26	wa_cve_2022_23960_bhb_vector_table NEOVERSE_POSEIDON_BHB_LOOP_COUNT, neoverse_poseidon
27#endif /* WORKAROUND_CVE_2022_23960 */
28
29	/* ---------------------------------------------
30	 * HW will do the cache maintenance while powering down
31	 * ---------------------------------------------
32	 */
33func neoverse_poseidon_core_pwr_dwn
34	/* ---------------------------------------------
35	 * Enable CPU power down bit in power control register
36	 * ---------------------------------------------
37	 */
38	mrs	x0, NEOVERSE_POSEIDON_CPUPWRCTLR_EL1
39	orr	x0, x0, #NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
40	msr	NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, x0
41	isb
42	ret
43endfunc neoverse_poseidon_core_pwr_dwn
44
45func check_errata_cve_2022_23960
46#if WORKAROUND_CVE_2022_23960
47	mov	x0, #ERRATA_APPLIES
48#else
49	mov	x0, #ERRATA_MISSING
50#endif
51	ret
52endfunc check_errata_cve_2022_23960
53
54func neoverse_poseidon_reset_func
55	/* Disable speculative loads */
56	msr	SSBS, xzr
57
58#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
59	/*
60	 * The Neoverse Poseidon generic vectors are overridden to apply
61	 * errata mitigation on exception entry from lower ELs.
62	 */
63	adr	x0, wa_cve_vbar_neoverse_poseidon
64	msr	vbar_el3, x0
65#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
66
67	isb
68	ret
69endfunc neoverse_poseidon_reset_func
70
71#if REPORT_ERRATA
72	/*
73	 * Errata printing function for Neoverse Poseidon. Must follow AAPCS.
74	 */
75func neoverse_poseidon_errata_report
76	stp	x8, x30, [sp, #-16]!
77
78	bl	cpu_get_rev_var
79	mov	x8, x0
80
81	/*
82	 * Report all errata. The revision-variant information is passed to
83	 * checking functions of each errata.
84	 */
85	report_errata WORKAROUND_CVE_2022_23960, neoverse_poseidon, cve_2022_23960
86
87	ldp	x8, x30, [sp], #16
88	ret
89endfunc neoverse_poseidon_errata_report
90#endif
91
92	/* ---------------------------------------------
93	 * This function provides Neoverse-Poseidon specific
94	 * register information for crash reporting.
95	 * It needs to return with x6 pointing to
96	 * a list of register names in ascii and
97	 * x8 - x15 having values of registers to be
98	 * reported.
99	 * ---------------------------------------------
100	 */
101.section .rodata.neoverse_poseidon_regs, "aS"
102neoverse_poseidon_regs:  /* The ascii list of register names to be reported */
103	.asciz	"cpuectlr_el1", ""
104
105func neoverse_poseidon_cpu_reg_dump
106	adr	x6, neoverse_poseidon_regs
107	mrs	x8, NEOVERSE_POSEIDON_CPUECTLR_EL1
108	ret
109endfunc neoverse_poseidon_cpu_reg_dump
110
111declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_MIDR, \
112	neoverse_poseidon_reset_func, \
113	neoverse_poseidon_core_pwr_dwn
114