1/*
2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <neoverse_v2.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
25#if WORKAROUND_CVE_2022_23960
26	wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
27#endif /* WORKAROUND_CVE_2022_23960 */
28
29	/* ----------------------------------------------------
30	 * HW will do the cache maintenance while powering down
31	 * ----------------------------------------------------
32	 */
33func neoverse_v2_core_pwr_dwn
34	/* ---------------------------------------------------
35	 * Enable CPU power down bit in power control register
36	 * ---------------------------------------------------
37	 */
38	mrs	x0, NEOVERSE_V2_CPUPWRCTLR_EL1
39	orr	x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
40	msr	NEOVERSE_V2_CPUPWRCTLR_EL1, x0
41	isb
42	ret
43endfunc neoverse_v2_core_pwr_dwn
44
45func check_errata_cve_2022_23960
46#if WORKAROUND_CVE_2022_23960
47	mov	x0, #ERRATA_APPLIES
48#else
49	mov	x0, #ERRATA_MISSING
50#endif
51	ret
52endfunc check_errata_cve_2022_23960
53
54func neoverse_v2_reset_func
55	/* Disable speculative loads */
56	msr	SSBS, xzr
57
58#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
59	/*
60	 * The Neoverse V2 vectors are overridden to apply
61	 * errata mitigation on exception entry from lower ELs.
62	 */
63	adr	x0, wa_cve_vbar_neoverse_v2
64	msr	vbar_el3, x0
65#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
66	isb
67	ret
68endfunc neoverse_v2_reset_func
69
70#if REPORT_ERRATA
71/*
72 * Errata printing function for Neoverse V2. Must follow AAPCS.
73 */
74func neoverse_v2_errata_report
75	stp	x8, x30, [sp, #-16]!
76
77	bl	cpu_get_rev_var
78	mov	x8, x0
79
80	/*
81	 * Report all errata. The revision-variant information is passed to
82	 * checking functions of each errata.
83	 */
84	report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960
85
86	ldp	x8, x30, [sp], #16
87	ret
88endfunc neoverse_v2_errata_report
89#endif
90
91	/* ---------------------------------------------
92	 * This function provides Neoverse V2-
93	 * specific register information for crash
94	 * reporting. It needs to return with x6
95	 * pointing to a list of register names in ascii
96	 * and x8 - x15 having values of registers to be
97	 * reported.
98	 * ---------------------------------------------
99	 */
100.section .rodata.neoverse_v2_regs, "aS"
101neoverse_v2_regs:  /* The ascii list of register names to be reported */
102	.asciz	"cpuectlr_el1", ""
103
104func neoverse_v2_cpu_reg_dump
105	adr	x6, neoverse_v2_regs
106	mrs	x8, NEOVERSE_V2_CPUECTLR_EL1
107	ret
108endfunc neoverse_v2_cpu_reg_dump
109
110declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
111	neoverse_v2_reset_func, \
112	neoverse_v2_core_pwr_dwn
113