1 /*
2  * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PLATFORM_DEF_H
8 #define PLATFORM_DEF_H
9 
10 #include <common/tbbr/tbbr_img_def.h>
11 #include <lib/utils_def.h>
12 #include <plat/common/common_def.h>
13 
14 #include <sunxi_mmap.h>
15 
16 #ifdef SUNXI_BL31_IN_DRAM
17 
18 #define BL31_BASE			SUNXI_DRAM_BASE
19 #define BL31_LIMIT			(SUNXI_DRAM_BASE + 0x40000)
20 
21 #define MAX_XLAT_TABLES			4
22 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
23 
24 #define SUNXI_BL33_VIRT_BASE		PRELOADED_BL33_BASE
25 
26 #else	/* !SUNXI_BL31_IN_DRAM */
27 
28 #define BL31_BASE			(SUNXI_SRAM_A2_BASE + \
29 					 SUNXI_SRAM_A2_BL31_OFFSET)
30 #define BL31_LIMIT			(SUNXI_SRAM_A2_BASE + \
31 					 SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE)
32 
33 /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
34 #define BL31_NOBITS_BASE		(SUNXI_SRAM_A1_BASE + 0x1000)
35 #define BL31_NOBITS_LIMIT		(SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE)
36 
37 #define MAX_XLAT_TABLES			1
38 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 28)
39 
40 #define SUNXI_BL33_VIRT_BASE		SUNXI_DRAM_VIRT_BASE
41 
42 /* The SCP firmware is allocated the last 16KiB of SRAM A2. */
43 #define SUNXI_SCP_BASE			BL31_LIMIT
44 #define SUNXI_SCP_SIZE			0x4000
45 
46 #endif /* SUNXI_BL31_IN_DRAM */
47 
48 /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */
49 #define SUNXI_DRAM_MAP_SIZE		(64U << 20)
50 
51 #define CACHE_WRITEBACK_SHIFT		6
52 #define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
53 
54 #define MAX_STATIC_MMAP_REGIONS		3
55 #define MAX_MMAP_REGIONS		(5 + MAX_STATIC_MMAP_REGIONS)
56 
57 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
58 	(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
59 
60 /* These states are used directly for SCPI communication. */
61 #define PLAT_MAX_PWR_LVL_STATES		U(3)
62 #define PLAT_MAX_RET_STATE		U(1)
63 #define PLAT_MAX_OFF_STATE		U(3)
64 
65 #define PLAT_MAX_PWR_LVL		U(2)
66 #define PLAT_NUM_PWR_DOMAINS		(U(1) + \
67 					 PLATFORM_CLUSTER_COUNT + \
68 					 PLATFORM_CORE_COUNT)
69 
70 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
71 
72 #define PLATFORM_CLUSTER_COUNT		U(1)
73 #define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER_COUNT * \
74 					 PLATFORM_MAX_CPUS_PER_CLUSTER)
75 #define PLATFORM_MAX_CPUS_PER_CLUSTER	U(4)
76 #define PLATFORM_STACK_SIZE		(0x1000 / PLATFORM_CORE_COUNT)
77 
78 #ifndef SPD_none
79 #ifndef BL32_BASE
80 #define BL32_BASE			SUNXI_DRAM_BASE
81 #endif
82 #endif
83 
84 #endif /* PLATFORM_DEF_H */
85