1 /*
2  * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef AXG_DEF_H
8 #define AXG_DEF_H
9 
10 #include <lib/utils_def.h>
11 
12 /*******************************************************************************
13  * System oscillator
14  ******************************************************************************/
15 #define AML_OSC24M_CLK_IN_HZ			ULL(24000000) /* 24 MHz */
16 
17 /*******************************************************************************
18  * Memory regions
19  ******************************************************************************/
20 #define AML_NS_SHARE_MEM_BASE			UL(0x05000000)
21 #define AML_NS_SHARE_MEM_SIZE			UL(0x00100000)
22 
23 #define AML_SEC_SHARE_MEM_BASE			UL(0x05200000)
24 #define AML_SEC_SHARE_MEM_SIZE			UL(0x00100000)
25 
26 #define AML_GIC_DEVICE_BASE			UL(0xFFC00000)
27 #define AML_GIC_DEVICE_SIZE			UL(0x00008000)
28 
29 #define AML_NSDRAM0_BASE			UL(0x01000000)
30 #define AML_NSDRAM0_SIZE			UL(0x0F000000)
31 
32 #define BL31_BASE				UL(0x05100000)
33 #define BL31_SIZE				UL(0x00100000)
34 #define BL31_LIMIT				(BL31_BASE + BL31_SIZE)
35 
36 /* Shared memory used for SMC services */
37 #define AML_SHARE_MEM_INPUT_BASE		UL(0x050FE000)
38 #define AML_SHARE_MEM_OUTPUT_BASE		UL(0x050FF000)
39 
40 #define AML_SEC_DEVICE0_BASE			UL(0xFFD00000)
41 #define AML_SEC_DEVICE0_SIZE			UL(0x00026000)
42 
43 #define AML_SEC_DEVICE1_BASE			UL(0xFF800000)
44 #define AML_SEC_DEVICE1_SIZE			UL(0x0000A000)
45 
46 #define AML_SEC_DEVICE2_BASE			UL(0xFF620000)
47 #define AML_SEC_DEVICE2_SIZE			UL(0x00028000)
48 
49 #define AML_TZRAM_BASE				UL(0xFFFC0000)
50 #define AML_TZRAM_SIZE				UL(0x00020000)
51 
52 /* Mailboxes */
53 #define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD	UL(0xFFFD3800)
54 #define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD	UL(0xFFFD3A00)
55 #define AML_PSCI_MAILBOX_BASE			UL(0xFFFD3F00)
56 
57 /*******************************************************************************
58  * GIC-400 and interrupt handling related constants
59  ******************************************************************************/
60 #define AML_GICD_BASE				UL(0xFFC01000)
61 #define AML_GICC_BASE				UL(0xFFC02000)
62 
63 #define IRQ_SEC_PHY_TIMER			29
64 
65 #define IRQ_SEC_SGI_0				8
66 #define IRQ_SEC_SGI_1				9
67 #define IRQ_SEC_SGI_2				10
68 #define IRQ_SEC_SGI_3				11
69 #define IRQ_SEC_SGI_4				12
70 #define IRQ_SEC_SGI_5				13
71 #define IRQ_SEC_SGI_6				14
72 #define IRQ_SEC_SGI_7				15
73 #define IRQ_SEC_SGI_8				16
74 
75 /*******************************************************************************
76  * UART definitions
77  ******************************************************************************/
78 #define AML_UART0_AO_BASE			UL(0xFF803000)
79 #define AML_UART0_AO_CLK_IN_HZ			AML_OSC24M_CLK_IN_HZ
80 #define AML_UART_BAUDRATE			U(115200)
81 
82 /*******************************************************************************
83  * Memory-mapped I/O Registers
84  ******************************************************************************/
85 #define AML_AO_TIMESTAMP_CNTL			UL(0xFF8000B4)
86 
87 #define AML_SYS_CPU_CFG7			UL(0xFF634664)
88 
89 #define AML_AO_RTI_STATUS_REG3			UL(0xFF80001C)
90 #define AML_AO_RTI_SCP_STAT			UL(0xFF80023C)
91 #define AML_AO_RTI_SCP_READY_OFF		U(0x14)
92 #define AML_A0_RTI_SCP_READY_MASK		U(3)
93 #define AML_AO_RTI_SCP_IS_READY(v)					\
94 	((((v) >> AML_AO_RTI_SCP_READY_OFF) &				\
95 	AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK)
96 
97 #define AML_HIU_MAILBOX_SET_0			UL(0xFF63C404)
98 #define AML_HIU_MAILBOX_STAT_0			UL(0xFF63C408)
99 #define AML_HIU_MAILBOX_CLR_0			UL(0xFF63C40C)
100 #define AML_HIU_MAILBOX_SET_3			UL(0xFF63C428)
101 #define AML_HIU_MAILBOX_STAT_3			UL(0xFF63C42C)
102 #define AML_HIU_MAILBOX_CLR_3			UL(0xFF63C430)
103 
104 #define AML_SHA_DMA_BASE			UL(0xFF63E000)
105 #define AML_SHA_DMA_DESC			(AML_SHA_DMA_BASE + 0x08)
106 #define AML_SHA_DMA_STATUS			(AML_SHA_DMA_BASE + 0x28)
107 
108 /*******************************************************************************
109  * System Monitor Call IDs and arguments
110  ******************************************************************************/
111 #define AML_SM_GET_SHARE_MEM_INPUT_BASE		U(0x82000020)
112 #define AML_SM_GET_SHARE_MEM_OUTPUT_BASE	U(0x82000021)
113 
114 #define AML_SM_EFUSE_READ			U(0x82000030)
115 #define AML_SM_EFUSE_USER_MAX			U(0x82000033)
116 
117 #define AML_SM_JTAG_ON				U(0x82000040)
118 #define AML_SM_JTAG_OFF				U(0x82000041)
119 #define AML_SM_GET_CHIP_ID			U(0x82000044)
120 
121 #define AML_JTAG_STATE_ON			U(0)
122 #define AML_JTAG_STATE_OFF			U(1)
123 
124 #define AML_JTAG_M3_AO				U(0)
125 #define AML_JTAG_M3_EE				U(1)
126 #define AML_JTAG_A53_AO				U(2)
127 #define AML_JTAG_A53_EE				U(3)
128 
129 #endif /* AXG_DEF_H */
130