1/*
2 * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <platform_def.h>
10
11	.globl	plat_secondary_cold_boot_setup
12	.globl	plat_get_my_entrypoint
13	.globl	plat_is_my_cpu_primary
14	.globl	plat_arm_calc_core_pos
15
16	/* --------------------------------------------------------------------
17	 * void plat_secondary_cold_boot_setup (void);
18	 *
19	 * For AArch32, cold-booting secondary CPUs is not yet
20	 * implemented and they panic.
21	 * --------------------------------------------------------------------
22	 */
23func plat_secondary_cold_boot_setup
24cb_panic:
25	b	cb_panic
26endfunc plat_secondary_cold_boot_setup
27
28	/* ---------------------------------------------------------------------
29	 * unsigned long plat_get_my_entrypoint (void);
30	 *
31	 * Main job of this routine is to distinguish between a cold and warm
32	 * boot. On Corstone700, this information can be queried from the power
33	 * controller. The Power Control SYS Status Register (PSYSR) indicates
34	 * the wake-up reason for the CPU.
35	 *
36	 * For a cold boot, return 0.
37	 * For a warm boot, Not yet supported.
38	 *
39	 * TODO: PSYSR is a common register and should be
40	 * 	accessed using locks. Since it is not possible
41	 * 	to use locks immediately after a cold reset
42	 * 	we are relying on the fact that after a cold
43	 * 	reset all cpus will read the same WK field
44	 * ---------------------------------------------------------------------
45	 */
46func plat_get_my_entrypoint
47	/* TODO support warm boot */
48	/* Cold reset */
49	mov	r0, #0
50	bx	lr
51endfunc plat_get_my_entrypoint
52
53	/* -----------------------------------------------------
54	 * unsigned int plat_is_my_cpu_primary (void);
55	 *
56	 * Find out whether the current CPU is the primary
57	 * CPU.
58	 * -----------------------------------------------------
59	 */
60func plat_is_my_cpu_primary
61	ldcopr	r0, MPIDR
62	ldr	r1, =MPIDR_AFFINITY_MASK
63	and	r0, r1
64	cmp	r0, #0
65	moveq	r0, #1
66	movne	r0, #0
67	bx	lr
68endfunc plat_is_my_cpu_primary
69
70	/* ---------------------------------------------------------------------
71	 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
72	 *
73	 * Function to calculate the core position on Corstone700.
74	 *
75	 * (ClusterId * MAX_CPUS_PER_CLUSTER * MAX_PE_PER_CPU) +
76	 * (CPUId * MAX_PE_PER_CPU) +
77	 * ThreadId
78	 *
79	 * which can be simplified as:
80	 *
81	 * ((ClusterId * MAX_CPUS_PER_CLUSTER + CPUId) * MAX_PE_PER_CPU)
82	 * + ThreadId
83	 * ---------------------------------------------------------------------
84	 */
85func plat_arm_calc_core_pos
86	mov	r3, r0
87
88	/* Extract individual affinity fields from MPIDR */
89	ubfx	r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
90	ubfx	r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
91	ubfx	r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
92
93	/* Compute linear position */
94	mov	r3, #CORSTONE700_MAX_CPUS_PER_CLUSTER
95	mla	r1, r2, r3, r1
96	mov	r3, #CORSTONE700_MAX_PE_PER_CPU
97	mla	r0, r1, r3, r0
98
99	bx	lr
100endfunc plat_arm_calc_core_pos
101