1 /* 2 * Copyright (c) 2018-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef N1SDP_DEF_H 8 #define N1SDP_DEF_H 9 10 /* Non-secure SRAM MMU mapping */ 11 #define N1SDP_NS_SRAM_BASE (0x06000000) 12 #define N1SDP_NS_SRAM_SIZE (0x00010000) 13 #define N1SDP_MAP_NS_SRAM MAP_REGION_FLAT( \ 14 N1SDP_NS_SRAM_BASE, \ 15 N1SDP_NS_SRAM_SIZE, \ 16 MT_DEVICE | MT_RW | MT_SECURE) 17 18 /* SDS Platform information defines */ 19 #define N1SDP_SDS_PLATFORM_INFO_STRUCT_ID 8 20 #define N1SDP_SDS_PLATFORM_INFO_OFFSET 0 21 #define N1SDP_SDS_PLATFORM_INFO_SIZE 4 22 #define N1SDP_MAX_DDR_CAPACITY_GB 64 23 #define N1SDP_MAX_SECONDARY_COUNT 16 24 25 /* DMC memory command registers */ 26 #define N1SDP_DMC0_MEMC_CMD_REG 0x4E000008 27 #define N1SDP_DMC1_MEMC_CMD_REG 0x4E100008 28 29 /* DMC ERR0CTLR0 registers */ 30 #define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708 31 #define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708 32 33 /* Remote DMC memory command registers */ 34 #define N1SDP_REMOTE_DMC0_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 35 N1SDP_DMC0_MEMC_CMD_REG 36 #define N1SDP_REMOTE_DMC1_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 37 N1SDP_DMC1_MEMC_CMD_REG 38 39 /* Remote DMC ERR0CTLR0 registers */ 40 #define N1SDP_REMOTE_DMC0_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 41 N1SDP_DMC0_ERR0CTLR0_REG 42 #define N1SDP_REMOTE_DMC1_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 43 N1SDP_DMC1_ERR0CTLR0_REG 44 45 /* DMC memory commands */ 46 #define N1SDP_DMC_MEMC_CMD_CONFIG 0 47 #define N1SDP_DMC_MEMC_CMD_READY 3 48 49 /* DMC ECC enable bit in ERR0CTLR0 register */ 50 #define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1 51 52 #endif /* N1SDP_DEF_H */ 53