1 /*
2 * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <plat/arm/common/plat_arm.h>
9 #include <platform_def.h>
10
11 /* TZC memory regions for the first chip */
12 static const arm_tzc_regions_info_t tzc_regions[] = {
13 ARM_TZC_REGIONS_DEF,
14 {}
15 };
16
17 #if CSS_SGI_CHIP_COUNT > 1
18 static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
19 {
20 /* TZC memory regions for second chip */
21 SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
22 {}
23 },
24 #if CSS_SGI_CHIP_COUNT > 2
25 {
26 /* TZC memory regions for third chip */
27 SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
28 {}
29 },
30 #endif
31 #if CSS_SGI_CHIP_COUNT > 3
32 {
33 /* TZC memory regions for fourth chip */
34 SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
35 {}
36 },
37 #endif
38 };
39 #endif /* CSS_SGI_CHIP_COUNT */
40
41 /* Initialize the secure environment */
plat_arm_security_setup(void)42 void plat_arm_security_setup(void)
43 {
44 unsigned int i;
45
46 INFO("Configuring TrustZone Controller for Chip 0\n");
47
48 for (i = 0; i < TZC400_COUNT; i++) {
49 arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
50 }
51
52 #if CSS_SGI_CHIP_COUNT > 1
53 unsigned int j;
54
55 for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) {
56 INFO("Configuring TrustZone Controller for Chip %u\n", i);
57
58 for (j = 0; j < TZC400_COUNT; j++) {
59 arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
60 + TZC400_BASE(j), tzc_regions_mc[i-1]);
61 }
62 }
63 #endif
64 }
65