1 /*
2 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <bl1/bl1.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <lib/fconf/fconf.h>
16 #include <lib/fconf/fconf_dyn_cfg_getter.h>
17 #include <lib/utils.h>
18 #include <lib/xlat_tables/xlat_tables_compat.h>
19 #include <plat/arm/common/plat_arm.h>
20 #include <plat/common/platform.h>
21
22 /* Weak definitions may be overridden in specific ARM standard platform */
23 #pragma weak bl1_early_platform_setup
24 #pragma weak bl1_plat_arch_setup
25 #pragma weak bl1_plat_sec_mem_layout
26 #pragma weak arm_bl1_early_platform_setup
27 #pragma weak bl1_plat_prepare_exit
28 #pragma weak bl1_plat_get_next_image_id
29 #pragma weak plat_arm_bl1_fwu_needed
30 #pragma weak arm_bl1_plat_arch_setup
31 #pragma weak arm_bl1_platform_setup
32
33 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \
34 bl1_tzram_layout.total_base, \
35 bl1_tzram_layout.total_size, \
36 MT_MEMORY | MT_RW | EL3_PAS)
37 /*
38 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
39 * otherwise one region is defined containing both
40 */
41 #if SEPARATE_CODE_AND_RODATA
42 #define MAP_BL1_RO MAP_REGION_FLAT( \
43 BL_CODE_BASE, \
44 BL1_CODE_END - BL_CODE_BASE, \
45 MT_CODE | EL3_PAS), \
46 MAP_REGION_FLAT( \
47 BL1_RO_DATA_BASE, \
48 BL1_RO_DATA_END \
49 - BL_RO_DATA_BASE, \
50 MT_RO_DATA | EL3_PAS)
51 #else
52 #define MAP_BL1_RO MAP_REGION_FLAT( \
53 BL_CODE_BASE, \
54 BL1_CODE_END - BL_CODE_BASE, \
55 MT_CODE | EL3_PAS)
56 #endif
57
58 /* Data structure which holds the extents of the trusted SRAM for BL1*/
59 static meminfo_t bl1_tzram_layout;
60
61 /* Boolean variable to hold condition whether firmware update needed or not */
62 static bool is_fwu_needed;
63
bl1_plat_sec_mem_layout(void)64 struct meminfo *bl1_plat_sec_mem_layout(void)
65 {
66 return &bl1_tzram_layout;
67 }
68
69 /*******************************************************************************
70 * BL1 specific platform actions shared between ARM standard platforms.
71 ******************************************************************************/
arm_bl1_early_platform_setup(void)72 void arm_bl1_early_platform_setup(void)
73 {
74
75 #if !ARM_DISABLE_TRUSTED_WDOG
76 /* Enable watchdog */
77 plat_arm_secure_wdt_start();
78 #endif
79
80 /* Initialize the console to provide early debug support */
81 arm_console_boot_init();
82
83 /* Allow BL1 to see the whole Trusted RAM */
84 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
85 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
86 }
87
bl1_early_platform_setup(void)88 void bl1_early_platform_setup(void)
89 {
90 arm_bl1_early_platform_setup();
91
92 /*
93 * Initialize Interconnect for this cluster during cold boot.
94 * No need for locks as no other CPU is active.
95 */
96 plat_arm_interconnect_init();
97 /*
98 * Enable Interconnect coherency for the primary CPU's cluster.
99 */
100 plat_arm_interconnect_enter_coherency();
101 }
102
103 /******************************************************************************
104 * Perform the very early platform specific architecture setup shared between
105 * ARM standard platforms. This only does basic initialization. Later
106 * architectural setup (bl1_arch_setup()) does not do anything platform
107 * specific.
108 *****************************************************************************/
arm_bl1_plat_arch_setup(void)109 void arm_bl1_plat_arch_setup(void)
110 {
111 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
112 /*
113 * Ensure ARM platforms don't use coherent memory in BL1 unless
114 * cryptocell integration is enabled.
115 */
116 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
117 #endif
118
119 const mmap_region_t bl_regions[] = {
120 MAP_BL1_TOTAL,
121 MAP_BL1_RO,
122 #if USE_ROMLIB
123 ARM_MAP_ROMLIB_CODE,
124 ARM_MAP_ROMLIB_DATA,
125 #endif
126 #if ARM_CRYPTOCELL_INTEG
127 ARM_MAP_BL_COHERENT_RAM,
128 #endif
129 {0}
130 };
131
132 setup_page_tables(bl_regions, plat_arm_get_mmap());
133 #ifdef __aarch64__
134 enable_mmu_el3(0);
135 #else
136 enable_mmu_svc_mon(0);
137 #endif /* __aarch64__ */
138
139 arm_setup_romlib();
140 }
141
bl1_plat_arch_setup(void)142 void bl1_plat_arch_setup(void)
143 {
144 arm_bl1_plat_arch_setup();
145 }
146
147 /*
148 * Perform the platform specific architecture setup shared between
149 * ARM standard platforms.
150 */
arm_bl1_platform_setup(void)151 void arm_bl1_platform_setup(void)
152 {
153 const struct dyn_cfg_dtb_info_t *fw_config_info;
154 image_desc_t *desc;
155 uint32_t fw_config_max_size;
156 int err = -1;
157
158 /* Initialise the IO layer and register platform IO devices */
159 plat_arm_io_setup();
160
161 /* Check if we need FWU before further processing */
162 is_fwu_needed = plat_arm_bl1_fwu_needed();
163 if (is_fwu_needed) {
164 ERROR("Skip platform setup as FWU detected\n");
165 return;
166 }
167
168 /* Set global DTB info for fixed fw_config information */
169 fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
170 set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, FW_CONFIG_ID);
171
172 /* Fill the device tree information struct with the info from the config dtb */
173 err = fconf_load_config(FW_CONFIG_ID);
174 if (err < 0) {
175 ERROR("Loading of FW_CONFIG failed %d\n", err);
176 plat_error_handler(err);
177 }
178
179 /*
180 * FW_CONFIG loaded successfully. If FW_CONFIG device tree parsing
181 * is successful then load TB_FW_CONFIG device tree.
182 */
183 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
184 if (fw_config_info != NULL) {
185 err = fconf_populate_dtb_registry(fw_config_info->config_addr);
186 if (err < 0) {
187 ERROR("Parsing of FW_CONFIG failed %d\n", err);
188 plat_error_handler(err);
189 }
190 /* load TB_FW_CONFIG */
191 err = fconf_load_config(TB_FW_CONFIG_ID);
192 if (err < 0) {
193 ERROR("Loading of TB_FW_CONFIG failed %d\n", err);
194 plat_error_handler(err);
195 }
196 } else {
197 ERROR("Invalid FW_CONFIG address\n");
198 plat_error_handler(err);
199 }
200
201 /* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
202 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
203 assert(desc != NULL);
204 desc->ep_info.args.arg0 = fw_config_info->config_addr;
205
206 #if CRYPTO_SUPPORT
207 /* Share the Mbed TLS heap info with other images */
208 arm_bl1_set_mbedtls_heap();
209 #endif /* CRYPTO_SUPPORT */
210
211 /*
212 * Allow access to the System counter timer module and program
213 * counter frequency for non secure images during FWU
214 */
215 #ifdef ARM_SYS_TIMCTL_BASE
216 arm_configure_sys_timer();
217 #endif
218 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
219 write_cntfrq_el0(plat_get_syscnt_freq2());
220 #endif
221 }
222
bl1_plat_prepare_exit(entry_point_info_t * ep_info)223 void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
224 {
225 #if !ARM_DISABLE_TRUSTED_WDOG
226 /* Disable watchdog before leaving BL1 */
227 plat_arm_secure_wdt_stop();
228 #endif
229
230 #ifdef EL3_PAYLOAD_BASE
231 /*
232 * Program the EL3 payload's entry point address into the CPUs mailbox
233 * in order to release secondary CPUs from their holding pen and make
234 * them jump there.
235 */
236 plat_arm_program_trusted_mailbox(ep_info->pc);
237 dsbsy();
238 sev();
239 #endif
240 }
241
242 /*
243 * On Arm platforms, the FWU process is triggered when the FIP image has
244 * been tampered with.
245 */
plat_arm_bl1_fwu_needed(void)246 bool plat_arm_bl1_fwu_needed(void)
247 {
248 return !arm_io_is_toc_valid();
249 }
250
251 /*******************************************************************************
252 * The following function checks if Firmware update is needed,
253 * by checking if TOC in FIP image is valid or not.
254 ******************************************************************************/
bl1_plat_get_next_image_id(void)255 unsigned int bl1_plat_get_next_image_id(void)
256 {
257 return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
258 }
259