1 /*
2 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <libfdt.h>
10
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <drivers/arm/css/css_mhu_doorbell.h>
14 #include <drivers/arm/css/scmi.h>
15 #include <plat/arm/common/plat_arm.h>
16
17 #include <plat/common/platform.h>
18
19 #include <plat/arm/css/common/css_pm.h>
20
21 #include <sgi_ras.h>
22 #include <sgi_variant.h>
23
24 sgi_platform_info_t sgi_plat_info;
25
26 static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
27 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
28 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
29 .db_preserve_mask = 0xfffffffe,
30 .db_modify_mask = 0x1,
31 .ring_doorbell = &mhu_ring_doorbell,
32 };
33
34 static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
35 {
36 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
37 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
38 .db_preserve_mask = 0xfffffffe,
39 .db_modify_mask = 0x1,
40 .ring_doorbell = &mhuv2_ring_doorbell,
41 },
42 #if (CSS_SGI_CHIP_COUNT > 1)
43 {
44 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
45 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
46 .db_reg_addr = PLAT_CSS_MHU_BASE
47 + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1) + SENDER_REG_SET(0),
48 .db_preserve_mask = 0xfffffffe,
49 .db_modify_mask = 0x1,
50 .ring_doorbell = &mhuv2_ring_doorbell,
51 },
52 #endif
53 #if (CSS_SGI_CHIP_COUNT > 2)
54 {
55 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
56 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
57 .db_reg_addr = PLAT_CSS_MHU_BASE +
58 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2) + SENDER_REG_SET(0),
59 .db_preserve_mask = 0xfffffffe,
60 .db_modify_mask = 0x1,
61 .ring_doorbell = &mhuv2_ring_doorbell,
62 },
63 #endif
64 #if (CSS_SGI_CHIP_COUNT > 3)
65 {
66 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
67 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
68 .db_reg_addr = PLAT_CSS_MHU_BASE +
69 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3) + SENDER_REG_SET(0),
70 .db_preserve_mask = 0xfffffffe,
71 .db_modify_mask = 0x1,
72 .ring_doorbell = &mhuv2_ring_doorbell,
73 },
74 #endif
75 };
76
plat_css_get_scmi_info(int channel_id)77 scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
78 {
79 if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
80 sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
81 sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
82 sgi_plat_info.platform_id == RD_V2_SID_VER_PART_NUM ||
83 sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) {
84 if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info))
85 panic();
86 return &plat_rd_scmi_info[channel_id];
87 }
88 else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM)
89 return &sgi575_scmi_plat_info;
90 else
91 panic();
92 }
93
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)94 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
95 u_register_t arg2, u_register_t arg3)
96 {
97 sgi_plat_info.platform_id = plat_arm_sgi_get_platform_id();
98 sgi_plat_info.config_id = plat_arm_sgi_get_config_id();
99 sgi_plat_info.multi_chip_mode = plat_arm_sgi_get_multi_chip_mode();
100
101 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
102 }
103
sgi_bl31_common_platform_setup(void)104 void sgi_bl31_common_platform_setup(void)
105 {
106 arm_bl31_platform_setup();
107
108 #if RAS_EXTENSION
109 sgi_ras_intr_handler_setup();
110 #endif
111
112 /* Configure the warm reboot SGI for primary core */
113 css_setup_cpu_pwr_down_intr();
114
115 #if CSS_SYSTEM_GRACEFUL_RESET
116 /* Register priority level handlers for reboot */
117 ehf_register_priority_handler(PLAT_REBOOT_PRI,
118 css_reboot_interrupt_handler);
119 #endif
120 }
121
plat_arm_psci_override_pm_ops(plat_psci_ops_t * ops)122 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
123 {
124 /*
125 * For RD-E1-Edge, only CPU power ON/OFF, PSCI platform callbacks are
126 * supported.
127 */
128 if (((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
129 (sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID))) {
130 ops->cpu_standby = NULL;
131 ops->system_off = NULL;
132 ops->system_reset = NULL;
133 ops->get_sys_suspend_power_state = NULL;
134 ops->pwr_domain_suspend = NULL;
135 ops->pwr_domain_suspend_finish = NULL;
136 }
137
138 return css_scmi_override_pm_ops(ops);
139 }
140