1 /*
2  * Copyright (c) 2015 - 2020, Broadcom
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CMN_PLAT_DEF_H
8 #define CMN_PLAT_DEF_H
9 
10 #include <bcm_elog.h>
11 #include <platform_def.h>
12 
13 #ifndef GET_LOG_LEVEL
14 #define GET_LOG_LEVEL() LOG_LEVEL
15 #endif
16 
17 #ifndef SET_LOG_LEVEL
18 #define SET_LOG_LEVEL(x) ((void)(x))
19 #endif
20 
21 #define PLAT_LOG_NOTICE(...)						 \
22 		do {							 \
23 			if (GET_LOG_LEVEL() >= LOG_LEVEL_NOTICE) {	 \
24 				bcm_elog(LOG_MARKER_NOTICE __VA_ARGS__); \
25 				tf_log(LOG_MARKER_NOTICE __VA_ARGS__);	 \
26 			}						 \
27 		} while (0)
28 
29 #define PLAT_LOG_ERROR(...)						 \
30 		do {							 \
31 			if (GET_LOG_LEVEL() >= LOG_LEVEL_ERROR) {	 \
32 				bcm_elog(LOG_MARKER_ERROR, __VA_ARGS__); \
33 				tf_log(LOG_MARKER_ERROR __VA_ARGS__);	 \
34 			}						 \
35 		} while (0)
36 
37 #define PLAT_LOG_WARN(...)						 \
38 		do {							 \
39 			if (GET_LOG_LEVEL() >= LOG_LEVEL_WARNING) {	 \
40 				bcm_elog(LOG_MARKER_WARNING, __VA_ARGS__);\
41 				tf_log(LOG_MARKER_WARNING __VA_ARGS__);	 \
42 			}						 \
43 		} while (0)
44 
45 #define PLAT_LOG_INFO(...)						 \
46 		do {							 \
47 			if (GET_LOG_LEVEL() >= LOG_LEVEL_INFO) {	 \
48 				bcm_elog(LOG_MARKER_INFO __VA_ARGS__);	 \
49 				tf_log(LOG_MARKER_INFO  __VA_ARGS__);    \
50 			}						 \
51 		} while (0)
52 
53 #define PLAT_LOG_VERBOSE(...)						 \
54 		do {							 \
55 			if (GET_LOG_LEVEL()  >= LOG_LEVEL_VERBOSE) {	 \
56 				bcm_elog(LOG_MARKER_VERBOSE __VA_ARGS__);\
57 				tf_log(LOG_MARKER_VERBOSE __VA_ARGS__);	 \
58 			}						 \
59 		} while (0)
60 
61 /*
62  * The number of regions like RO(code), coherent and data required by
63  * different BL stages which need to be mapped in the MMU.
64  */
65 #if USE_COHERENT_MEM
66 #define CMN_BL_REGIONS	3
67 #else
68 #define CMN_BL_REGIONS	2
69 #endif
70 
71 /*
72  * FIP definitions
73  */
74 #define PLAT_FIP_ATTEMPT_OFFSET		0x20000
75 #define PLAT_FIP_NUM_ATTEMPTS		128
76 
77 #define PLAT_BRCM_FIP_QSPI_BASE		QSPI_BASE_ADDR
78 #define PLAT_BRCM_FIP_NAND_BASE		NAND_BASE_ADDR
79 #define PLAT_BRCM_FIP_MAX_SIZE		0x01000000
80 
81 #define PLAT_BRCM_FIP_BASE	PLAT_BRCM_FIP_QSPI_BASE
82 #endif
83