1 /*
2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdbool.h>
8
9 #include <arch.h>
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/delay_timer.h>
13 #include <lib/mmio.h>
14 #include <lib/psci/psci.h>
15
16 #include <dram.h>
17 #include <gpc.h>
18 #include <imx8m_psci.h>
19 #include <plat_imx8.h>
20
21 /*
22 * below callback functions need to be override by i.mx8mq,
23 * for other i.mx8m soc, if no special requirement,
24 * reuse below ones.
25 */
26 #pragma weak imx_validate_power_state
27 #pragma weak imx_domain_suspend
28 #pragma weak imx_domain_suspend_finish
29 #pragma weak imx_get_sys_suspend_power_state
30
imx_validate_ns_entrypoint(uintptr_t ns_entrypoint)31 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint)
32 {
33 /* The non-secure entrypoint should be in RAM space */
34 if (ns_entrypoint < PLAT_NS_IMAGE_OFFSET)
35 return PSCI_E_INVALID_PARAMS;
36
37 return PSCI_E_SUCCESS;
38 }
39
imx_pwr_domain_on(u_register_t mpidr)40 int imx_pwr_domain_on(u_register_t mpidr)
41 {
42 unsigned int core_id;
43 uint64_t base_addr = BL31_START;
44
45 core_id = MPIDR_AFFLVL0_VAL(mpidr);
46
47 imx_set_cpu_secure_entry(core_id, base_addr);
48 imx_set_cpu_pwr_on(core_id);
49
50 return PSCI_E_SUCCESS;
51 }
52
imx_pwr_domain_on_finish(const psci_power_state_t * target_state)53 void imx_pwr_domain_on_finish(const psci_power_state_t *target_state)
54 {
55 plat_gic_pcpu_init();
56 plat_gic_cpuif_enable();
57 }
58
imx_pwr_domain_off(const psci_power_state_t * target_state)59 void imx_pwr_domain_off(const psci_power_state_t *target_state)
60 {
61 uint64_t mpidr = read_mpidr_el1();
62 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
63
64 plat_gic_cpuif_disable();
65 imx_set_cpu_pwr_off(core_id);
66 }
67
imx_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)68 int imx_validate_power_state(unsigned int power_state,
69 psci_power_state_t *req_state)
70 {
71 int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
72 int pwr_type = psci_get_pstate_type(power_state);
73 int state_id = psci_get_pstate_id(power_state);
74
75 if (pwr_lvl > PLAT_MAX_PWR_LVL)
76 return PSCI_E_INVALID_PARAMS;
77
78 if (pwr_type == PSTATE_TYPE_STANDBY) {
79 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
80 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
81 }
82
83 if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) {
84 CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE;
85 CLUSTER_PWR_STATE(req_state) = PLAT_WAIT_RET_STATE;
86 }
87
88 return PSCI_E_SUCCESS;
89 }
90
imx_cpu_standby(plat_local_state_t cpu_state)91 void imx_cpu_standby(plat_local_state_t cpu_state)
92 {
93 dsb();
94 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
95 isb();
96
97 wfi();
98
99 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT));
100 isb();
101 }
102
imx_domain_suspend(const psci_power_state_t * target_state)103 void imx_domain_suspend(const psci_power_state_t *target_state)
104 {
105 uint64_t base_addr = BL31_START;
106 uint64_t mpidr = read_mpidr_el1();
107 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
108
109 if (is_local_state_off(CORE_PWR_STATE(target_state))) {
110 plat_gic_cpuif_disable();
111 imx_set_cpu_secure_entry(core_id, base_addr);
112 imx_set_cpu_lpm(core_id, true);
113 } else {
114 dsb();
115 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
116 isb();
117 }
118
119 if (!is_local_state_run(CLUSTER_PWR_STATE(target_state)))
120 imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state));
121
122 if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) {
123 imx_set_sys_lpm(core_id, true);
124 dram_enter_retention();
125 imx_anamix_override(true);
126 }
127 }
128
imx_domain_suspend_finish(const psci_power_state_t * target_state)129 void imx_domain_suspend_finish(const psci_power_state_t *target_state)
130 {
131 uint64_t mpidr = read_mpidr_el1();
132 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
133
134 if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) {
135 imx_anamix_override(false);
136 dram_exit_retention();
137 imx_set_sys_lpm(core_id, false);
138 }
139
140 if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) {
141 imx_clear_rbc_count();
142 imx_set_cluster_powerdown(core_id, PSCI_LOCAL_STATE_RUN);
143 }
144
145 if (is_local_state_off(CORE_PWR_STATE(target_state))) {
146 imx_set_cpu_lpm(core_id, false);
147 plat_gic_cpuif_enable();
148 } else {
149 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT));
150 isb();
151 }
152 }
153
imx_get_sys_suspend_power_state(psci_power_state_t * req_state)154 void imx_get_sys_suspend_power_state(psci_power_state_t *req_state)
155 {
156 unsigned int i;
157
158 for (i = IMX_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
159 req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE;
160 }
161
imx_wdog_restart(bool external_reset)162 static void __dead2 imx_wdog_restart(bool external_reset)
163 {
164 uintptr_t wdog_base = IMX_WDOG_BASE;
165 unsigned int val;
166
167 val = mmio_read_16(wdog_base);
168 /*
169 * Common watchdog init flags, for additional details check
170 * 6.6.4.1 Watchdog Control Register (WDOGx_WCR)
171 *
172 * Initial bit selection:
173 * WDOG_WCR_WDE - Enable the watchdog.
174 *
175 * 0x000E mask is used to keep previous values (that could be set
176 * in SPL) of WDBG and WDE/WDT (both are write-one once-only bits).
177 */
178 val = (val & 0x000E) | WDOG_WCR_WDE;
179 if (external_reset) {
180 /*
181 * To assert WDOG_B (external reset) we have
182 * to set WDA bit 0 (already set in previous step).
183 * SRS bits are required to be set to 1 (no effect on the
184 * system).
185 */
186 val |= WDOG_WCR_SRS;
187 } else {
188 /*
189 * To assert Software Reset Signal (internal reset) we have
190 * to set SRS bit to 0 (already set in previous step).
191 * SRE bit is required to be set to 1 when used in
192 * conjunction with the Software Reset Signal before
193 * SRS asserton, otherwise SRS bit will just automatically
194 * reset to 1.
195 *
196 * Also we set WDA to 1 (no effect on system).
197 */
198 val |= WDOG_WCR_SRE | WDOG_WCR_WDA;
199 }
200
201 mmio_write_16(wdog_base, val);
202
203 mmio_write_16(wdog_base + WDOG_WSR, 0x5555);
204 mmio_write_16(wdog_base + WDOG_WSR, 0xaaaa);
205 while (1)
206 ;
207 }
208
imx_system_reset(void)209 void __dead2 imx_system_reset(void)
210 {
211 #ifdef IMX_WDOG_B_RESET
212 imx_wdog_restart(true);
213 #else
214 imx_wdog_restart(false);
215 #endif
216 }
217
imx_system_reset2(int is_vendor,int reset_type,u_register_t cookie)218 int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
219 {
220 imx_wdog_restart(false);
221
222 /*
223 * imx_wdog_restart cannot return (as it's a __dead function),
224 * however imx_system_reset2 has to return some value according
225 * to PSCI v1.1 spec.
226 */
227 return 0;
228 }
229
imx_system_off(void)230 void __dead2 imx_system_off(void)
231 {
232 uint32_t val;
233
234 val = mmio_read_32(IMX_SNVS_BASE + SNVS_LPCR);
235 val |= SNVS_LPCR_SRTC_ENV | SNVS_LPCR_DP_EN | SNVS_LPCR_TOP;
236 mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, val);
237
238 while (1)
239 ;
240 }
241
imx_pwr_domain_pwr_down_wfi(const psci_power_state_t * target_state)242 void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
243 {
244 /*
245 * before enter WAIT or STOP mode with PLAT(SCU) power down,
246 * rbc count need to be enabled to make sure PLAT is
247 * power down successfully even if the the wakeup IRQ is pending
248 * early before the power down sequence. the RBC counter is
249 * drived by the 32K OSC, so delay 30us to make sure the counter
250 * is really running.
251 */
252 if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) {
253 imx_set_rbc_count();
254 udelay(30);
255 }
256
257 while (1)
258 wfi();
259 }
260