1 /*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdlib.h>
8 #include <stdint.h>
9 #include <stdbool.h>
10
11 #include <common/debug.h>
12 #include <drivers/delay_timer.h>
13 #include <lib/mmio.h>
14 #include <lib/psci/psci.h>
15 #include <platform_def.h>
16 #include <services/std_svc.h>
17
18 #include <gpc.h>
19
20 /* use wfi power down the core */
imx_set_cpu_pwr_off(unsigned int core_id)21 void imx_set_cpu_pwr_off(unsigned int core_id)
22 {
23 bakery_lock_get(&gpc_lock);
24
25 /* enable the wfi power down of the core */
26 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
27 (1 << (core_id + 20)));
28
29 bakery_lock_release(&gpc_lock);
30
31 /* assert the pcg pcr bit of the core */
32 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
33 };
34
35 /* if out of lpm, we need to do reverse steps */
imx_set_cpu_lpm(unsigned int core_id,bool pdn)36 void imx_set_cpu_lpm(unsigned int core_id, bool pdn)
37 {
38 bakery_lock_get(&gpc_lock);
39
40 if (pdn) {
41 /* enable the core WFI PDN & IRQ PUP */
42 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
43 (1 << (core_id + 20)) | COREx_IRQ_WUP(core_id));
44 /* assert the pcg pcr bit of the core */
45 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
46 } else {
47 /* disable CORE WFI PDN & IRQ PUP */
48 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
49 COREx_IRQ_WUP(core_id));
50 /* deassert the pcg pcr bit of the core */
51 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
52 }
53
54 bakery_lock_release(&gpc_lock);
55 }
56
imx_pup_pdn_slot_config(int last_core,bool pdn)57 void imx_pup_pdn_slot_config(int last_core, bool pdn)
58 {
59 if (pdn) {
60 /* SLOT0 for A53 PLAT power down */
61 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), SLT_PLAT_PDN);
62 /* SLOT1 for A53 PLAT power up */
63 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(1), SLT_PLAT_PUP);
64 /* SLOT2 for A53 primary core power up */
65 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), SLT_COREx_PUP(last_core));
66 /* ACK setting: PLAT ACK for PDN, CORE ACK for PUP */
67 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF,
68 A53_PLAT_PDN_ACK | A53_PLAT_PUP_ACK);
69 } else {
70 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF);
71 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF);
72 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), 0xFFFFFFFF);
73 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF,
74 A53_DUMMY_PDN_ACK | A53_DUMMY_PUP_ACK);
75 }
76 }
77
imx_set_cluster_powerdown(unsigned int last_core,uint8_t power_state)78 void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state)
79 {
80 uint32_t val;
81
82 if (is_local_state_off(power_state)) {
83 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
84 val |= A53_LPM_STOP; /* enable C0-C1's STOP mode */
85 val &= ~CPU_CLOCK_ON_LPM; /* disable CPU clock in LPM mode */
86 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
87
88 /* enable C2-3's STOP mode */
89 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_STOP);
90
91 /* enable PLAT/SCU power down */
92 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);
93 val &= ~EN_L2_WFI_PDN;
94 val |= L2PGE | EN_PLAT_PDN;
95 val &= ~COREx_IRQ_WUP(last_core); /* disable IRQ PUP for last core */
96 val |= COREx_LPM_PUP(last_core); /* enable LPM PUP for last core */
97 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);
98
99 imx_pup_pdn_slot_config(last_core, true);
100
101 /* enable PLAT PGC */
102 mmio_setbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1);
103 } else {
104 /* clear PLAT PGC */
105 mmio_clrbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1);
106
107 /* clear the slot and ack for cluster power down */
108 imx_pup_pdn_slot_config(last_core, false);
109
110 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
111 val &= ~A53_LPM_MASK; /* clear the C0~1 LPM */
112 val |= CPU_CLOCK_ON_LPM; /* disable cpu clock in LPM */
113 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
114
115 /* set A53 LPM to RUN mode */
116 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_MASK);
117
118 /* clear PLAT/SCU power down */
119 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);
120 val |= EN_L2_WFI_PDN;
121 val &= ~(L2PGE | EN_PLAT_PDN);
122 val &= ~COREx_LPM_PUP(last_core); /* disable C0's LPM PUP */
123 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);
124 }
125 }
126
imx_gpc_init(void)127 void imx_gpc_init(void)
128 {
129 uint32_t val;
130 int i;
131 /* mask all the interrupt by default */
132 for (i = 0; i < 4; i++) {
133 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
134 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
135 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
136 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
137 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
138 }
139 /* Due to the hardware design requirement, need to make
140 * sure GPR interrupt(#32) is unmasked during RUN mode to
141 * avoid entering DSM mode by mistake.
142 */
143 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53, 0xFFFFFFFE);
144 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53, 0xFFFFFFFE);
145 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53, 0xFFFFFFFE);
146 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53, 0xFFFFFFFE);
147
148 /* use external IRQs to wakeup C0~C3 from LPM */
149 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
150 val |= IRQ_SRC_A53_WUP;
151 /* clear the MASTER0 LPM handshake */
152 val &= ~MASTER0_LPM_HSK;
153 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
154
155 /* mask M4 DSM trigger if M4 is NOT enabled */
156 mmio_setbits_32(IMX_GPC_BASE + LPCR_M4, DSM_MODE_MASK);
157
158 /* set all mix/PU in A53 domain */
159 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd);
160
161 /* set SCU timming */
162 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
163 (0x59 << 10) | 0x5B | (0x2 << 20));
164
165 /* set DUMMY PDN/PUP ACK by default for A53 domain */
166 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK |
167 A53_DUMMY_PDN_ACK);
168
169 /* disable DSM mode by default */
170 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, DSM_MODE_MASK);
171
172 /*
173 * USB PHY power up needs to make sure RESET bit in SRC is clear,
174 * otherwise, the PU power up bit in GPC will NOT self-cleared.
175 * only need to do it once.
176 */
177 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
178 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
179
180 /*
181 * for USB OTG, the limitation are:
182 * 1. before system clock config, the IPG clock run at 12.5MHz, delay time
183 * should be longer than 82us.
184 * 2. after system clock config, ipg clock run at 66.5MHz, delay time
185 * be longer that 15.3 us.
186 * Add 100us to make sure the USB OTG SRC is clear safely.
187 */
188 udelay(100);
189 }
190