1 /* 2 * Copyright 2019-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DRAM_H 8 #define DRAM_H 9 10 #include <assert.h> 11 12 #include <arch_helpers.h> 13 #include <lib/utils_def.h> 14 15 #include <ddrc.h> 16 #include <platform_def.h> 17 18 #define DDRC_LPDDR4 BIT(5) 19 #define DDRC_DDR4 BIT(4) 20 #define DDRC_DDR3L BIT(0) 21 #define DDR_TYPE_MASK U(0x3f) 22 #define ACTIVE_RANK_MASK U(0x3) 23 24 /* reg & config param */ 25 struct dram_cfg_param { 26 unsigned int reg; 27 unsigned int val; 28 }; 29 30 struct dram_timing_info { 31 /* umctl2 config */ 32 struct dram_cfg_param *ddrc_cfg; 33 unsigned int ddrc_cfg_num; 34 /* ddrphy config */ 35 struct dram_cfg_param *ddrphy_cfg; 36 unsigned int ddrphy_cfg_num; 37 /* ddr fsp train info */ 38 struct dram_fsp_msg *fsp_msg; 39 unsigned int fsp_msg_num; 40 /* ddr phy trained CSR */ 41 struct dram_cfg_param *ddrphy_trained_csr; 42 unsigned int ddrphy_trained_csr_num; 43 /* ddr phy PIE */ 44 struct dram_cfg_param *ddrphy_pie; 45 unsigned int ddrphy_pie_num; 46 /* initialized fsp table */ 47 unsigned int fsp_table[4]; 48 }; 49 50 struct dram_info { 51 int dram_type; 52 unsigned int num_rank; 53 uint32_t num_fsp; 54 int current_fsp; 55 int boot_fsp; 56 bool bypass_mode; 57 struct dram_timing_info *timing_info; 58 /* mr, emr, emr2, emr3, mr11, mr12, mr22, mr14 */ 59 uint32_t mr_table[3][8]; 60 }; 61 62 extern struct dram_info dram_info; 63 64 void dram_info_init(unsigned long dram_timing_base); 65 void dram_umctl2_init(struct dram_timing_info *timing); 66 void dram_phy_init(struct dram_timing_info *timing); 67 68 /* dram retention */ 69 void dram_enter_retention(void); 70 void dram_exit_retention(void); 71 72 void dram_clock_switch(unsigned int target_drate, bool bypass_mode); 73 74 /* dram frequency change */ 75 void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, unsigned int fsp_index); 76 void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate); 77 78 #endif /* DRAM_H */ 79