1 /*
2  * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef SOCFPGA_PRIVATE_H
8 #define SOCFPGA_PRIVATE_H
9 
10 #include "socfpga_plat_def.h"
11 
12 #define EMMC_DESC_SIZE		(1<<20)
13 
14 #define EMMC_INIT_PARAMS(base, clk)			\
15 	{	.bus_width = MMC_BUS_WIDTH_4,		\
16 		.clk_rate = (clk),			\
17 		.desc_base = (base),			\
18 		.desc_size = EMMC_DESC_SIZE,		\
19 		.flags = 0,				\
20 		.reg_base = SOCFPGA_MMC_REG_BASE	\
21 	}
22 
23 typedef enum {
24 	BOOT_SOURCE_FPGA = 0,
25 	BOOT_SOURCE_SDMMC,
26 	BOOT_SOURCE_NAND,
27 	BOOT_SOURCE_RSVD,
28 	BOOT_SOURCE_QSPI
29 } boot_source_type;
30 
31 /*******************************************************************************
32  * Function and variable prototypes
33  ******************************************************************************/
34 
35 void enable_nonsecure_access(void);
36 
37 void socfpga_io_setup(int boot_source);
38 
39 void socfgpa_configure_mmu_el3(unsigned long total_base,
40 			unsigned long total_size,
41 			unsigned long ro_start,
42 			unsigned long ro_limit,
43 			unsigned long coh_start,
44 			unsigned long coh_limit);
45 
46 
47 void socfpga_configure_mmu_el1(unsigned long total_base,
48 			unsigned long total_size,
49 			unsigned long ro_start,
50 			unsigned long ro_limit,
51 			unsigned long coh_start,
52 			unsigned long coh_limit);
53 
54 void socfpga_delay_timer_init(void);
55 
56 void socfpga_gic_driver_init(void);
57 
58 void socfpga_delay_timer_init_args(void);
59 
60 uint32_t socfpga_get_spsr_for_bl32_entry(void);
61 
62 uint32_t socfpga_get_spsr_for_bl33_entry(void);
63 
64 unsigned long socfpga_get_ns_image_entrypoint(void);
65 
66 void plat_secondary_cpus_bl31_entry(void);
67 
68 #endif /* SOCFPGA_PRIVATE_H */
69