1 /*
2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <arch.h>
9 #include <arch_helpers.h>
10 #include <assert.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <common/desc_image_load.h>
14 #include <drivers/generic_delay_timer.h>
15 #include <drivers/synopsys/dw_mmc.h>
16 #include <drivers/ti/uart/uart_16550.h>
17 #include <lib/xlat_tables/xlat_tables.h>
18
19 #include "qspi/cadence_qspi.h"
20 #include "socfpga_emac.h"
21 #include "socfpga_f2sdram_manager.h"
22 #include "socfpga_handoff.h"
23 #include "socfpga_mailbox.h"
24 #include "socfpga_private.h"
25 #include "socfpga_reset_manager.h"
26 #include "socfpga_system_manager.h"
27 #include "s10_clock_manager.h"
28 #include "s10_memory_controller.h"
29 #include "s10_mmc.h"
30 #include "s10_pinmux.h"
31 #include "wdt/watchdog.h"
32
33 static struct mmc_device_info mmc_info;
34
35 const mmap_region_t plat_stratix10_mmap[] = {
36 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
37 MT_MEMORY | MT_RW | MT_NS),
38 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
39 MT_DEVICE | MT_RW | MT_NS),
40 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
41 MT_DEVICE | MT_RW | MT_SECURE),
42 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
43 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
44 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
45 MT_DEVICE | MT_RW | MT_SECURE),
46 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
47 MT_DEVICE | MT_RW | MT_NS),
48 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
49 MT_DEVICE | MT_RW | MT_NS),
50 {0},
51 };
52
53 boot_source_type boot_source = BOOT_SOURCE;
54
bl2_el3_early_platform_setup(u_register_t x0,u_register_t x1,u_register_t x2,u_register_t x4)55 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
56 u_register_t x2, u_register_t x4)
57 {
58 static console_t console;
59 handoff reverse_handoff_ptr;
60
61 generic_delay_timer_init();
62
63 if (socfpga_get_handoff(&reverse_handoff_ptr))
64 return;
65 config_pinmux(&reverse_handoff_ptr);
66
67 config_clkmgr_handoff(&reverse_handoff_ptr);
68 enable_nonsecure_access();
69 deassert_peripheral_reset();
70 config_hps_hs_before_warm_reset();
71
72 watchdog_init(get_wdt_clk());
73
74 console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(),
75 PLAT_BAUDRATE, &console);
76
77 socfpga_emac_init();
78 socfpga_delay_timer_init();
79 init_hard_memory_controller();
80 mailbox_init();
81 s10_mmc_init();
82
83 if (!intel_mailbox_is_fpga_not_ready()) {
84 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK |
85 FPGA2SOC_MASK | F2SDRAM0_MASK | F2SDRAM1_MASK |
86 F2SDRAM2_MASK);
87 }
88 }
89
90
bl2_el3_plat_arch_setup(void)91 void bl2_el3_plat_arch_setup(void)
92 {
93
94 const mmap_region_t bl_regions[] = {
95 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
96 MT_MEMORY | MT_RW | MT_SECURE),
97 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
98 MT_CODE | MT_SECURE),
99 MAP_REGION_FLAT(BL_RO_DATA_BASE,
100 BL_RO_DATA_END - BL_RO_DATA_BASE,
101 MT_RO_DATA | MT_SECURE),
102 #if USE_COHERENT_MEM_BAR
103 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
104 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
105 MT_DEVICE | MT_RW | MT_SECURE),
106 #endif
107 {0},
108 };
109
110 setup_page_tables(bl_regions, plat_stratix10_mmap);
111
112 enable_mmu_el3(0);
113
114 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
115
116 mmc_info.mmc_dev_type = MMC_IS_SD;
117 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
118
119 /* Request ownership and direct access to QSPI */
120 mailbox_hps_qspi_enable();
121
122 switch (boot_source) {
123 case BOOT_SOURCE_SDMMC:
124 dw_mmc_init(¶ms, &mmc_info);
125 socfpga_io_setup(boot_source);
126 break;
127
128 case BOOT_SOURCE_QSPI:
129 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
130 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
131 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
132 socfpga_io_setup(boot_source);
133 break;
134
135 default:
136 ERROR("Unsupported boot source\n");
137 panic();
138 break;
139 }
140 }
141
get_spsr_for_bl33_entry(void)142 uint32_t get_spsr_for_bl33_entry(void)
143 {
144 unsigned long el_status;
145 unsigned int mode;
146 uint32_t spsr;
147
148 /* Figure out what mode we enter the non-secure world in */
149 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
150 el_status &= ID_AA64PFR0_ELX_MASK;
151
152 mode = (el_status) ? MODE_EL2 : MODE_EL1;
153
154 /*
155 * TODO: Consider the possibility of specifying the SPSR in
156 * the FIP ToC and allowing the platform to have a say as
157 * well.
158 */
159 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
160 return spsr;
161 }
162
163
bl2_plat_handle_post_image_load(unsigned int image_id)164 int bl2_plat_handle_post_image_load(unsigned int image_id)
165 {
166 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
167
168 assert(bl_mem_params);
169
170 switch (image_id) {
171 case BL33_IMAGE_ID:
172 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
173 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
174 break;
175 default:
176 break;
177 }
178
179 return 0;
180 }
181
182 /*******************************************************************************
183 * Perform any BL3-1 platform setup code
184 ******************************************************************************/
bl2_platform_setup(void)185 void bl2_platform_setup(void)
186 {
187 }
188
189