1 /*
2  * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PLAT_SOCFPGA_DEF_H
8 #define PLAT_SOCFPGA_DEF_H
9 
10 #include <platform_def.h>
11 
12 /* Platform Setting */
13 #define PLATFORM_MODEL				PLAT_SOCFPGA_STRATIX10
14 #define BOOT_SOURCE				BOOT_SOURCE_SDMMC
15 
16 /* FPGA config helpers */
17 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR		0x400000
18 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE		0x1000000
19 
20 /* Register Mapping */
21 #define SOCFPGA_CCU_NOC_REG_BASE		0xf7000000
22 #define SOCFPGA_F2SDRAMMGR_REG_BASE		U(0xf8024000)
23 
24 #define SOCFPGA_MMC_REG_BASE                    0xff808000
25 
26 #define SOCFPGA_RSTMGR_REG_BASE			0xffd11000
27 #define SOCFPGA_SYSMGR_REG_BASE			0xffd12000
28 
29 #define SOCFPGA_L4_PER_SCR_REG_BASE		0xffd21000
30 #define SOCFPGA_L4_SYS_SCR_REG_BASE		0xffd21100
31 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE		0xffd21200
32 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE		0xffd21300
33 
34 /* Platform specific system counter */
35 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ	get_cpu_clk()
36 
37 uint32_t get_cpu_clk(void);
38 
39 #endif /* PLATSOCFPGA_DEF_H */
40 
41