1 /*
2  * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MT_CPU_PM_H
8 #define MT_CPU_PM_H
9 
10 #include <assert.h>
11 #include <mcucfg.h>
12 #include <platform_def.h>
13 
14 /*
15  * After ARM v8.2, the cache will turn off automatically when powering down CPU. Therefore, there
16  * is no doubt to use the spin_lock here.
17  */
18 #if !HW_ASSISTED_COHERENCY
19 #define MT_CPU_PM_USING_BAKERY_LOCK
20 #endif
21 
22 #define CPU_PM_FN (MTK_CPUPM_FN_CPUPM_GET_PWR_STATE | \
23 		   MTK_CPUPM_FN_PWR_STATE_VALID | \
24 		   MTK_CPUPM_FN_PWR_ON_CORE_PREPARE | \
25 		   MTK_CPUPM_FN_RESUME_CORE | \
26 		   MTK_CPUPM_FN_SUSPEND_MCUSYS | \
27 		   MTK_CPUPM_FN_RESUME_MCUSYS | \
28 		   MTK_CPUPM_FN_SMP_INIT | \
29 		   MTK_CPUPM_FN_SMP_CORE_ON | \
30 		   MTK_CPUPM_FN_SMP_CORE_OFF)
31 
32 #define CPU_PM_ASSERT(_cond) ({ \
33 	if (!(_cond)) { \
34 		INFO("[%s:%d] - %s\n", __func__, __LINE__, #_cond); \
35 		panic(); \
36 	} })
37 
38 #define CPC_PWR_MASK_MCUSYS_MP0		(0xC001)
39 
40 #define PER_CPU_PWR_DATA(ctrl, cluster, core) \
41 	do { \
42 		ctrl.rvbaraddr_l = CORE_RVBRADDR_##cluster##_##core##_L; \
43 		ctrl.arch_addr = MCUCFG_MP0_CLUSTER_CFG5; \
44 		ctrl.pwpr = SPM_MP##cluster##_CPU##core##_PWR_CON; \
45 	} while (0)
46 
47 #define PER_CPU_PWR_CTRL(ctrl, cpu) ({ \
48 	switch (cpu) { \
49 	case 0: \
50 		PER_CPU_PWR_DATA(ctrl, 0, 0); \
51 		break; \
52 	case 1: \
53 		PER_CPU_PWR_DATA(ctrl, 0, 1); \
54 		break; \
55 	case 2: \
56 		PER_CPU_PWR_DATA(ctrl, 0, 2); \
57 		break; \
58 	case 3: \
59 		PER_CPU_PWR_DATA(ctrl, 0, 3); \
60 		break; \
61 	case 4: \
62 		PER_CPU_PWR_DATA(ctrl, 0, 4); \
63 		break; \
64 	case 5: \
65 		PER_CPU_PWR_DATA(ctrl, 0, 5); \
66 		break; \
67 	case 6: \
68 		PER_CPU_PWR_DATA(ctrl, 0, 6); \
69 		break; \
70 	case 7: \
71 		PER_CPU_PWR_DATA(ctrl, 0, 7); \
72 		break; \
73 	default: \
74 		assert(0); \
75 		break; \
76 	} })
77 
78 
79 /* MCUSYS DREQ BIG VPROC ISO control */
80 #define DREQ20_BIG_VPROC_ISO		(MCUCFG_BASE + 0xad8c)
81 
82 /* Definition about bootup address for each core CORE_RVBRADDR_clusterid_cpuid */
83 #define CORE_RVBRADDR_0_0_L		(MCUCFG_BASE + 0xc900)
84 #define CORE_RVBRADDR_0_1_L		(MCUCFG_BASE + 0xc908)
85 #define CORE_RVBRADDR_0_2_L		(MCUCFG_BASE + 0xc910)
86 #define CORE_RVBRADDR_0_3_L		(MCUCFG_BASE + 0xc918)
87 #define CORE_RVBRADDR_0_4_L		(MCUCFG_BASE + 0xc920)
88 #define CORE_RVBRADDR_0_5_L		(MCUCFG_BASE + 0xc928)
89 #define CORE_RVBRADDR_0_6_L		(MCUCFG_BASE + 0xc930)
90 #define CORE_RVBRADDR_0_7_L		(MCUCFG_BASE + 0xc938)
91 #define MCUCFG_MP0_CLUSTER_CFG5		(MCUCFG_BASE + 0xc8e4)
92 
93 struct cpu_pwr_ctrl {
94 	unsigned int rvbaraddr_l;
95 	unsigned int arch_addr;
96 	unsigned int pwpr;
97 };
98 
99 #define MCUSYS_STATUS_PDN		BIT(0)
100 #define MCUSYS_STATUS_CPUSYS_PROTECT	BIT(8)
101 #define MCUSYS_STATUS_MCUSYS_PROTECT	BIT(9)
102 
103 /* cpu_pm function ID */
104 enum mt_cpu_pm_user_id {
105 	MCUSYS_STATUS,
106 	CPC_COMMAND,
107 };
108 
109 /* cpu_pm lp function ID */
110 enum mt_cpu_pm_lp_smc_id {
111 	LP_CPC_COMMAND,
112 	IRQS_REMAIN_ALLOC,
113 	IRQS_REMAIN_CTRL,
114 	IRQS_REMAIN_IRQ,
115 	IRQS_REMAIN_WAKEUP_CAT,
116 	IRQS_REMAIN_WAKEUP_SRC,
117 };
118 
119 #endif /* MT_CPU_PM_H */
120