1 /* 2 * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef EMI_MPU_PRIV_H 8 #define EMI_MPU_PRIV_H 9 10 #define ENABLE_EMI_MPU_SW_LOCK (1) 11 12 #define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000) 13 #define EMI_MPU_DBG (EMI_MPU_BASE + 0x004) 14 #define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100) 15 #define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200) 16 #define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region * 4)) 17 #define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region * 4)) 18 #define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300) 19 #define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100)) 20 #define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800) 21 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) 22 #define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900) 23 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) 24 25 #define SUB_EMI_MPU_CTRL (SUB_EMI_MPU_BASE + 0x000) 26 #define SUB_EMI_MPU_DBG (SUB_EMI_MPU_BASE + 0x004) 27 #define SUB_EMI_MPU_SA0 (SUB_EMI_MPU_BASE + 0x100) 28 #define SUB_EMI_MPU_EA0 (SUB_EMI_MPU_BASE + 0x200) 29 #define SUB_EMI_MPU_SA(region) (SUB_EMI_MPU_SA0 + (region * 4)) 30 #define SUB_EMI_MPU_EA(region) (SUB_EMI_MPU_EA0 + (region * 4)) 31 #define SUB_EMI_MPU_APC0 (SUB_EMI_MPU_BASE + 0x300) 32 #define SUB_EMI_MPU_APC(region, dgroup) (SUB_EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100)) 33 #define SUB_EMI_MPU_CTRL_D0 (SUB_EMI_MPU_BASE + 0x800) 34 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) 35 #define SUB_EMI_RG_MASK_D0 (SUB_EMI_MPU_BASE + 0x900) 36 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) 37 38 #define EMI_MPU_DOMAIN_NUM (16) 39 #define EMI_MPU_REGION_NUM (32) 40 #define EMI_MPU_ALIGN_BITS (16) 41 #define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS) 42 43 #define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8) 44 45 #endif 46