1 /* 2 * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef RTC_H 8 #define RTC_H 9 10 /* RTC registers */ 11 enum { 12 RTC_BBPU = 0x0588, 13 RTC_IRQ_STA = 0x058A, 14 RTC_IRQ_EN = 0x058C, 15 RTC_CII_EN = 0x058E 16 }; 17 18 enum { 19 RTC_AL_SEC = 0x05A0, 20 RTC_AL_MIN = 0x05A2, 21 RTC_AL_HOU = 0x05A4, 22 RTC_AL_DOM = 0x05A6, 23 RTC_AL_DOW = 0x05A8, 24 RTC_AL_MTH = 0x05AA, 25 RTC_AL_YEA = 0x05AC, 26 RTC_AL_MASK = 0x0590 27 }; 28 29 enum { 30 RTC_OSC32CON = 0x05AE, 31 RTC_CON = 0x05C4, 32 RTC_WRTGR = 0x05C2 33 }; 34 35 enum { 36 RTC_PDN1 = 0x05B4, 37 RTC_PDN2 = 0x05B6, 38 RTC_SPAR0 = 0x05B8, 39 RTC_SPAR1 = 0x05BA, 40 RTC_PROT = 0x05BC, 41 RTC_DIFF = 0x05BE, 42 RTC_CALI = 0x05C0 43 }; 44 45 enum { 46 RTC_OSC32CON_UNLOCK1 = 0x1A57, 47 RTC_OSC32CON_UNLOCK2 = 0x2B68 48 }; 49 50 enum { 51 RTC_PROT_UNLOCK1 = 0x586A, 52 RTC_PROT_UNLOCK2 = 0x9136 53 }; 54 55 enum { 56 RTC_BBPU_PWREN = 1U << 0, 57 RTC_BBPU_CLR = 1U << 1, 58 RTC_BBPU_INIT = 1U << 2, 59 RTC_BBPU_AUTO = 1U << 3, 60 RTC_BBPU_CLRPKY = 1U << 4, 61 RTC_BBPU_RELOAD = 1U << 5, 62 RTC_BBPU_CBUSY = 1U << 6 63 }; 64 65 enum { 66 RTC_AL_MASK_SEC = 1U << 0, 67 RTC_AL_MASK_MIN = 1U << 1, 68 RTC_AL_MASK_HOU = 1U << 2, 69 RTC_AL_MASK_DOM = 1U << 3, 70 RTC_AL_MASK_DOW = 1U << 4, 71 RTC_AL_MASK_MTH = 1U << 5, 72 RTC_AL_MASK_YEA = 1U << 6 73 }; 74 75 enum { 76 RTC_BBPU_AUTO_PDN_SEL = 1U << 6, 77 RTC_BBPU_2SEC_CK_SEL = 1U << 7, 78 RTC_BBPU_2SEC_EN = 1U << 8, 79 RTC_BBPU_2SEC_MODE = 0x3 << 9, 80 RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11, 81 RTC_BBPU_2SEC_STAT_STA = 1U << 12 82 }; 83 84 enum { 85 RTC_BBPU_KEY = 0x43 << 8 86 }; 87 88 enum { 89 RTC_EMBCK_SRC_SEL = 1 << 8, 90 RTC_EMBCK_SEL_MODE = 3 << 6, 91 RTC_XOSC32_ENB = 1 << 5, 92 RTC_REG_XOSC32_ENB = 1 << 15 93 }; 94 95 enum { 96 RTC_K_EOSC_RSV_0 = 1 << 8, 97 RTC_K_EOSC_RSV_1 = 1 << 9, 98 RTC_K_EOSC_RSV_2 = 1 << 10 99 }; 100 101 /* PMIC TOP Register Definition */ 102 enum { 103 PMIC_RG_TOP_CON = 0x001E, 104 PMIC_RG_TOP_CKPDN_CON1 = 0x0112, 105 PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, 106 PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, 107 PMIC_RG_TOP_CKSEL_CON0 = 0x0118, 108 PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A, 109 PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C 110 }; 111 112 /* PMIC SCK Register Definition */ 113 enum { 114 PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x051A, 115 PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x051C, 116 PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x051E, 117 PMIC_RG_EOSC_CALI_CON0 = 0x540 118 }; 119 120 /* PMIC DCXO Register Definition */ 121 enum { 122 PMIC_RG_DCXO_CW00 = 0x0788, 123 PMIC_RG_DCXO_CW02 = 0x0790 124 }; 125 126 enum { 127 PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK = 0x1, 128 PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT = 1, 129 PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK = 0x1, 130 PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT = 3, 131 PMIC_RG_RTC_EOSC32_CK_PDN_MASK = 0x1, 132 PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT = 2, 133 PMIC_RG_EOSC_CALI_TD_MASK = 0x7, 134 PMIC_RG_EOSC_CALI_TD_SHIFT = 5, 135 PMIC_RG_XO_EN32K_MAN_MASK = 0x1, 136 PMIC_RG_XO_EN32K_MAN_SHIFT = 0 137 }; 138 139 /* external API */ 140 uint16_t RTC_Read(uint32_t addr); 141 void RTC_Write(uint32_t addr, uint16_t data); 142 int32_t rtc_busy_wait(void); 143 int32_t RTC_Write_Trigger(void); 144 int32_t Writeif_unlock(void); 145 void rtc_power_off_sequence(void); 146 147 #endif /* RTC_H */ 148