1 /*
2  * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PLAT_DFD_H
8 #define PLAT_DFD_H
9 
10 #include <arch_helpers.h>
11 #include <lib/mmio.h>
12 #include <platform_def.h>
13 
14 #define sync_writel(addr, val)	do { mmio_write_32((addr), (val)); \
15 				dsbsy(); \
16 				} while (0)
17 
18 #define PLAT_MTK_DFD_SETUP_MAGIC		(0x99716150)
19 #define PLAT_MTK_DFD_READ_MAGIC			(0x99716151)
20 #define PLAT_MTK_DFD_WRITE_MAGIC		(0x99716152)
21 
22 #define MCU_BIU_BASE				(MCUCFG_BASE)
23 #define MISC1_CFG_BASE				(MCU_BIU_BASE + 0xA040)
24 
25 #define DFD_INTERNAL_CTL			(MISC1_CFG_BASE + 0x00)
26 #define DFD_INTERNAL_PWR_ON			(MISC1_CFG_BASE + 0x08)
27 #define DFD_CHAIN_LENGTH0			(MISC1_CFG_BASE + 0x0C)
28 #define DFD_INTERNAL_SHIFT_CLK_RATIO		(MISC1_CFG_BASE + 0x10)
29 #define DFD_INTERNAL_TEST_SO_0			(MISC1_CFG_BASE + 0x28)
30 #define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP	(MISC1_CFG_BASE + 0x30)
31 #define DFD_V30_CTL				(MISC1_CFG_BASE + 0x48)
32 #define DFD_V30_BASE_ADDR			(MISC1_CFG_BASE + 0x4C)
33 #define DFD_TEST_SI_0				(MISC1_CFG_BASE + 0x58)
34 #define DFD_TEST_SI_1				(MISC1_CFG_BASE + 0x5C)
35 #define DFD_HW_TRIGGER_MASK			(MISC1_CFG_BASE + 0xBC)
36 
37 #define DFD_V35_ENALBE				(MCU_BIU_BASE + 0xA0A8)
38 #define DFD_V35_TAP_NUMBER			(MCU_BIU_BASE + 0xA0AC)
39 #define DFD_V35_TAP_EN				(MCU_BIU_BASE + 0xA0B0)
40 #define DFD_V35_SEQ0_0				(MCU_BIU_BASE + 0xA0C0)
41 #define DFD_V35_SEQ0_1				(MCU_BIU_BASE + 0xA0C4)
42 
43 #define DFD_CACHE_DUMP_ENABLE			(1U)
44 #define DFD_PARITY_ERR_TRIGGER			(2U)
45 
46 #define MCUSYS_DFD_MAP				(0x10001390)
47 #define WDT_DEBUG_CTL				(0x10007048)
48 
49 #define WDT_DEBUG_CTL_VAL_0			(0x950603A0)
50 #define DFD_INTERNAL_TEST_SO_0_VAL		(0x3B)
51 #define DFD_TEST_SI_0_VAL			(0x108)
52 #define DFD_TEST_SI_1_VAL			(0x20200000)
53 
54 #define WDT_DEBUG_CTL_VAL_1			(0x95063E80)
55 #define DFD_V35_TAP_NUMBER_VAL			(0xA)
56 #define DFD_V35_TAP_EN_VAL			(0x3FF)
57 #define DFD_V35_SEQ0_0_VAL			(0x63668820)
58 #define DFD_HW_TRIGGER_MASK_VAL			(0xC)
59 
60 void dfd_resume(void);
61 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
62 			    uint64_t arg2, uint64_t arg3);
63 
64 #endif /* PLAT_DFD_H */
65