1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_CPU_PM_CPC_H 8 #define MT_CPU_PM_CPC_H 9 10 #include <lib/mmio.h> 11 #include <lib/utils_def.h> 12 #include <mcucfg.h> 13 #include <platform_def.h> 14 15 #define NEED_CPUSYS_PROT_WORKAROUND 1 16 17 /* system sram registers */ 18 #define CPUIDLE_SRAM_REG(r) (0x11B000 + (r)) 19 20 /* db dump */ 21 #define CPC_TRACE_SIZE U(0x20) 22 #define CPC_TRACE_ID_NUM U(10) 23 #define CPC_TRACE_SRAM(id) (CPUIDLE_SRAM_REG(0x10) + (id) * CPC_TRACE_SIZE) 24 25 /* buckup off count */ 26 #define CPC_CLUSTER_CNT_BACKUP CPUIDLE_SRAM_REG(0x1F0) 27 #define CPC_MCUSYS_CNT CPUIDLE_SRAM_REG(0x1F4) 28 29 /* CPC_MCUSYS_CPC_FLOW_CTRL_CFG(0xA814): debug setting */ 30 #define CPC_PWR_ON_SEQ_DIS BIT(1) 31 #define CPC_PWR_ON_PRIORITY BIT(2) 32 #define CPC_AUTO_OFF_EN BIT(5) 33 #define CPC_DORMANT_WAIT_EN BIT(14) 34 #define CPC_CTRL_EN BIT(16) 35 #define CPC_OFF_PRE_EN BIT(29) 36 37 /* CPC_MCUSYS_LAST_CORE_REQ(0xA818) : last core protection */ 38 #define CPUSYS_PROT_SET BIT(0) 39 #define MCUSYS_PROT_SET BIT(8) 40 #define CPUSYS_PROT_CLR BIT(8) 41 #define MCUSYS_PROT_CLR BIT(9) 42 43 #define CPC_PROT_RESP_MASK U(0x3) 44 #define CPUSYS_RESP_OFS U(16) 45 #define MCUSYS_RESP_OFS U(30) 46 47 #define cpusys_resp(r) (((r) >> CPUSYS_RESP_OFS) & CPC_PROT_RESP_MASK) 48 #define mcusys_resp(r) (((r) >> MCUSYS_RESP_OFS) & CPC_PROT_RESP_MASK) 49 50 #define RETRY_CNT_MAX U(1000) 51 52 #define PROT_RETRY U(0) 53 #define PROT_SUCCESS U(1) 54 #define PROT_GIVEUP U(2) 55 56 /* CPC_MCUSYS_CPC_DBG_SETTING(0xAB00): debug setting */ 57 #define CPC_PROF_EN BIT(0) 58 #define CPC_DBG_EN BIT(1) 59 #define CPC_FREEZE BIT(2) 60 #define CPC_CALC_EN BIT(3) 61 62 enum { 63 CPC_SUCCESS = 0U, 64 CPC_ERR_FAIL = 1U, 65 CPC_ERR_TIMEOUT = 2U, 66 NF_CPC_ERR = 3U, 67 }; 68 69 enum { 70 CPC_SMC_EVENT_DUMP_TRACE_DATA = 0U, 71 CPC_SMC_EVENT_GIC_DPG_SET = 1U, 72 CPC_SMC_EVENT_CPC_CONFIG = 2U, 73 CPC_SMC_EVENT_READ_CONFIG = 3U, 74 NF_CPC_SMC_EVENT = 4U, 75 }; 76 77 enum { 78 CPC_SMC_CONFIG_PROF = 0U, 79 CPC_SMC_CONFIG_AUTO_OFF = 1U, 80 CPC_SMC_CONFIG_AUTO_OFF_THRES = 2U, 81 CPC_SMC_CONFIG_CNT_CLR = 3U, 82 CPC_SMC_CONFIG_TIME_SYNC = 4U, 83 NF_CPC_SMC_CONFIG = 5U, 84 }; 85 86 #define us_to_ticks(us) ((us) * 13) 87 #define ticks_to_us(tick) ((tick) / 13) 88 89 int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster); 90 void mtk_cpu_pm_cluster_prot_release(unsigned int cluster); 91 92 void mtk_cpc_mcusys_off_reflect(void); 93 int mtk_cpc_mcusys_off_prepare(void); 94 95 void mtk_cpc_core_on_hint_set(unsigned int cpu); 96 void mtk_cpc_core_on_hint_clr(unsigned int cpu); 97 void mtk_cpc_time_sync(void); 98 99 uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2); 100 void mtk_cpc_init(void); 101 102 #endif /* MT_CPU_PM_CPC_H */ 103