1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_CONSTRAINT_H 8 #define MT_SPM_CONSTRAINT_H 9 10 #include <mt_lp_rm.h> 11 12 #define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF BIT(0) 13 #define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 BIT(1) 14 #define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 BIT(2) 15 #define MT_RM_CONSTRAINT_ALLOW_VCORE_LP BIT(3) 16 #define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN BIT(4) 17 #define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF BIT(5) 18 #define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND BIT(6) 19 #define MT_RM_CONSTRAINT_ALLOW_BBLPM BIT(7) 20 #define MT_RM_CONSTRAINT_ALLOW_XO_UFS BIT(8) 21 #define MT_RM_CONSTRAINT_ALLOW_GPS_STATE BIT(9) 22 #define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE BIT(10) 23 24 #define MT_SPM_RC_INVALID (0x0) 25 #define MT_SPM_RC_VALID_SW BIT(0) 26 #define MT_SPM_RC_VALID_FW BIT(1) 27 #define MT_SPM_RC_VALID_RESIDNECY BIT(2) 28 #define MT_SPM_RC_VALID_COND_CHECK BIT(3) 29 #define MT_SPM_RC_VALID_COND_LATCH BIT(4) 30 #define MT_SPM_RC_VALID_UFS_H8 BIT(5) 31 #define MT_SPM_RC_VALID_FLIGHTMODE BIT(6) 32 #define MT_SPM_RC_VALID_XSOC_BBLPM BIT(7) 33 #define MT_SPM_RC_VALID_TRACE_EVENT BIT(8) 34 35 #define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW) 36 37 #define IS_MT_RM_RC_READY(status) \ 38 ((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID) 39 40 #define MT_SPM_RC_BBLPM_MODE \ 41 (MT_SPM_RC_VALID_UFS_H8 | \ 42 MT_SPM_RC_VALID_FLIGHTMODE | \ 43 MT_SPM_RC_VALID_XSOC_BBLPM) 44 45 #define IS_MT_SPM_RC_BBLPM_MODE(st) \ 46 ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE) 47 48 struct constraint_status { 49 uint16_t id; 50 uint16_t valid; 51 uint32_t cond_block; 52 uint32_t enter_cnt; 53 struct mt_spm_cond_tables *cond_res; 54 }; 55 56 enum MT_SPM_RM_RC_TYPE { 57 MT_RM_CONSTRAINT_ID_BUS26M = 0U, 58 MT_RM_CONSTRAINT_ID_SYSPLL = 1U, 59 MT_RM_CONSTRAINT_ID_DRAM = 2U, 60 MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO = 3U, 61 MT_RM_CONSTRAINT_ID_ALL = 4U, 62 }; 63 64 #endif /* MT_SPM_CONSTRAINT_H */ 65