1 /*
2  * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PLATFORM_DEF_H
8 #define PLATFORM_DEF_H
9 
10 #include <arch_def.h>
11 
12 #define PLAT_PRIMARY_CPU	(0x0)
13 
14 #define MT_GIC_BASE		(0x0C000000)
15 #define MCUCFG_BASE		(0x0C530000)
16 #define MCUCFG_REG_SIZE		(0x10000)
17 #define IO_PHYS			(0x10000000)
18 
19 /* Aggregate of all devices for MMU mapping */
20 #define MTK_DEV_RNG0_BASE	(MT_GIC_BASE)
21 #define MTK_DEV_RNG0_SIZE	(0x600000)
22 #define MTK_DEV_RNG1_BASE	(IO_PHYS)
23 #define MTK_DEV_RNG1_SIZE	(0x10000000)
24 
25 /*******************************************************************************
26  * AUDIO related constants
27  ******************************************************************************/
28 #define AUDIO_BASE		(IO_PHYS + 0x00b10000)
29 
30 /*******************************************************************************
31  * SPM related constants
32  ******************************************************************************/
33 #define SPM_BASE		(IO_PHYS + 0x00006000)
34 
35 /*******************************************************************************
36  * GPIO related constants
37  ******************************************************************************/
38 #define GPIO_BASE		(IO_PHYS + 0x00005000)
39 #define RGU_BASE		(IO_PHYS + 0x00007000)
40 #define DRM_BASE		(IO_PHYS + 0x0000D000)
41 #define IOCFG_RM_BASE		(IO_PHYS + 0x01C00000)
42 #define IOCFG_LT_BASE		(IO_PHYS + 0x01E10000)
43 #define IOCFG_LM_BASE		(IO_PHYS + 0x01E20000)
44 #define IOCFG_RT_BASE		(IO_PHYS + 0x01EA0000)
45 
46 /*******************************************************************************
47  * UART related constants
48  ******************************************************************************/
49 #define UART0_BASE	(IO_PHYS + 0x01002000)
50 #define UART_BAUDRATE	(115200)
51 
52 /*******************************************************************************
53  * PMIC related constants
54  ******************************************************************************/
55 #define PMIC_WRAP_BASE		(IO_PHYS + 0x00024000)
56 
57 /*******************************************************************************
58  * Infra IOMMU related constants
59  ******************************************************************************/
60 #define PERICFG_AO_BASE		(IO_PHYS + 0x01003000)
61 #define PERICFG_AO_REG_SIZE	(0x1000)
62 
63 /*******************************************************************************
64  * GIC-600 & interrupt handling related constants
65  ******************************************************************************/
66 /* Base MTK_platform compatible GIC memory map */
67 #define BASE_GICD_BASE		(MT_GIC_BASE)
68 #define MT_GIC_RDIST_BASE	(MT_GIC_BASE + 0x40000)
69 
70 /*******************************************************************************
71  * CIRQ related constants
72  ******************************************************************************/
73 #define SYS_CIRQ_BASE		(IO_PHYS + 0x204000)
74 #define MD_WDT_IRQ_BIT_ID	(141)
75 #define CIRQ_IRQ_NUM		(730)
76 #define CIRQ_REG_NUM		(23)
77 #define CIRQ_SPI_START		(96)
78 
79 /*******************************************************************************
80  * MM IOMMU & SMI related constants
81  ******************************************************************************/
82 #define SMI_LARB_0_BASE		(IO_PHYS + 0x0c022000)
83 #define SMI_LARB_1_BASE		(IO_PHYS + 0x0c023000)
84 #define SMI_LARB_2_BASE		(IO_PHYS + 0x0c102000)
85 #define SMI_LARB_3_BASE		(IO_PHYS + 0x0c103000)
86 #define SMI_LARB_4_BASE		(IO_PHYS + 0x04013000)
87 #define SMI_LARB_5_BASE		(IO_PHYS + 0x04f02000)
88 #define SMI_LARB_6_BASE		(IO_PHYS + 0x04f03000)
89 #define SMI_LARB_7_BASE		(IO_PHYS + 0x04e04000)
90 #define SMI_LARB_9_BASE		(IO_PHYS + 0x05001000)
91 #define SMI_LARB_10_BASE	(IO_PHYS + 0x05120000)
92 #define SMI_LARB_11A_BASE	(IO_PHYS + 0x05230000)
93 #define SMI_LARB_11B_BASE	(IO_PHYS + 0x05530000)
94 #define SMI_LARB_11C_BASE	(IO_PHYS + 0x05630000)
95 #define SMI_LARB_12_BASE	(IO_PHYS + 0x05340000)
96 #define SMI_LARB_13_BASE	(IO_PHYS + 0x06001000)
97 #define SMI_LARB_14_BASE	(IO_PHYS + 0x06002000)
98 #define SMI_LARB_15_BASE	(IO_PHYS + 0x05140000)
99 #define SMI_LARB_16A_BASE	(IO_PHYS + 0x06008000)
100 #define SMI_LARB_16B_BASE	(IO_PHYS + 0x0600a000)
101 #define SMI_LARB_17A_BASE	(IO_PHYS + 0x06009000)
102 #define SMI_LARB_17B_BASE	(IO_PHYS + 0x0600b000)
103 #define SMI_LARB_19_BASE	(IO_PHYS + 0x0a010000)
104 #define SMI_LARB_21_BASE	(IO_PHYS + 0x0802e000)
105 #define SMI_LARB_23_BASE	(IO_PHYS + 0x0800d000)
106 #define SMI_LARB_27_BASE	(IO_PHYS + 0x07201000)
107 #define SMI_LARB_28_BASE	(IO_PHYS + 0x00000000)
108 #define SMI_LARB_REG_RNG_SIZE	(0x1000)
109 
110 /*******************************************************************************
111  * DP related constants
112  ******************************************************************************/
113 #define EDP_SEC_BASE		(IO_PHYS + 0x0C504000)
114 #define DP_SEC_BASE		(IO_PHYS + 0x0C604000)
115 #define EDP_SEC_SIZE		(0x1000)
116 #define DP_SEC_SIZE		(0x1000)
117 
118 /*******************************************************************************
119  * EMI MPU related constants
120  *******************************************************************************/
121 #define EMI_MPU_BASE		(IO_PHYS + 0x00226000)
122 #define SUB_EMI_MPU_BASE	(IO_PHYS + 0x00225000)
123 
124 /*******************************************************************************
125  * System counter frequency related constants
126  ******************************************************************************/
127 #define SYS_COUNTER_FREQ_IN_HZ	(13000000)
128 #define SYS_COUNTER_FREQ_IN_MHZ	(13)
129 
130 /*******************************************************************************
131  * Platform binary types for linking
132  ******************************************************************************/
133 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
134 #define PLATFORM_LINKER_ARCH		aarch64
135 
136 /*******************************************************************************
137  * Generic platform constants
138  ******************************************************************************/
139 #define PLATFORM_STACK_SIZE		(0x800)
140 #define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
141 #define SOC_CHIP_ID			U(0x8188)
142 
143 /*******************************************************************************
144  * Platform memory map related constants
145  ******************************************************************************/
146 #define TZRAM_BASE			(0x54600000)
147 #define TZRAM_SIZE			(0x00030000)
148 
149 /*******************************************************************************
150  * BL31 specific defines.
151  ******************************************************************************/
152 /*
153  * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
154  * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
155  * little space for growth.
156  */
157 #define BL31_BASE			(TZRAM_BASE + 0x1000)
158 #define BL31_LIMIT			(TZRAM_BASE + TZRAM_SIZE)
159 
160 /*******************************************************************************
161  * Platform specific page table and MMU setup constants
162  ******************************************************************************/
163 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
164 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
165 #define MAX_XLAT_TABLES			(16)
166 #define MAX_MMAP_REGIONS		(16)
167 
168 /*******************************************************************************
169  * CPU_EB TCM handling related constants
170  ******************************************************************************/
171 #define CPU_EB_TCM_BASE		(0x0C550000)
172 #define CPU_EB_TCM_SIZE		(0x10000)
173 #define CPU_EB_MBOX3_OFFSET	(0xFCE0)
174 
175 /*******************************************************************************
176  * CPU PM definitions
177  *******************************************************************************/
178 #define PLAT_CPU_PM_B_BUCK_ISO_ID	(6)
179 #define PLAT_CPU_PM_ILDO_ID		(6)
180 #define CPU_IDLE_SRAM_BASE		(0x11B000)
181 #define CPU_IDLE_SRAM_SIZE		(0x1000)
182 
183 #endif /* PLATFORM_DEF_H */
184