1 /*
2 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8
9 #include <mt_lp_rm.h>
10 #include <mt_spm.h>
11 #include <mt_spm_cond.h>
12 #include <mt_spm_constraint.h>
13 #include <mt_spm_conservation.h>
14 #include <mt_spm_idle.h>
15 #include <mt_spm_internal.h>
16 #include <mt_spm_notifier.h>
17 #include <mt_spm_rc_internal.h>
18 #include <mt_spm_reg.h>
19 #include <mt_spm_resource_req.h>
20 #include <mt_spm_suspend.h>
21 #include <plat_pm.h>
22 #include <plat_mtk_lpm.h>
23
24 #define CONSTRAINT_SYSPLL_ALLOW \
25 (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
26 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
27 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
28 MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
29
30 #define CONSTRAINT_SYSPLL_PCM_FLAG \
31 (SPM_FLAG_DISABLE_INFRA_PDN | \
32 SPM_FLAG_DISABLE_VCORE_DVS | \
33 SPM_FLAG_DISABLE_VCORE_DFS | \
34 SPM_FLAG_SRAM_SLEEP_CTRL | \
35 SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
36 SPM_FLAG_ENABLE_6315_CTRL | \
37 SPM_FLAG_USE_SRCCLKENO2)
38
39 #define CONSTRAINT_SYSPLL_PCM_FLAG1 0U
40 #define CONSTRAINT_SYSPLL_RESOURCE_REQ \
41 (MT_SPM_26M)
42
43 static struct mt_spm_cond_tables cond_syspll = {
44 .name = "syspll",
45 .table_cg = {
46 0x078BF1FC, /* MTCMOS1 */
47 0x080D8856, /* INFRA0 */
48 0x03AF9A00, /* INFRA1 */
49 0x86000640, /* INFRA2 */
50 0xC800C000, /* INFRA3 */
51 0x00000000, /* INFRA4 */
52 0x0000007C, /* INFRA5 */
53 0x280E0800, /* MMSYS0 */
54 0x00000001, /* MMSYS1 */
55 0x00000000, /* MMSYS2 */
56 },
57 .table_pll = 0U,
58 };
59
60 static struct mt_spm_cond_tables cond_syspll_res = {
61 .table_cg = { 0U },
62 .table_pll = 0U,
63 };
64
65 static struct constraint_status status = {
66 .id = MT_RM_CONSTRAINT_ID_SYSPLL,
67 .valid = (MT_SPM_RC_VALID_SW |
68 MT_SPM_RC_VALID_COND_LATCH |
69 MT_SPM_RC_VALID_XSOC_BBLPM),
70 .cond_block = 0U,
71 .enter_cnt = 0U,
72 .cond_res = &cond_syspll_res,
73 };
74
spm_syspll_conduct(struct spm_lp_scen * spm_lp,unsigned int * resource_req)75 static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
76 unsigned int *resource_req)
77 {
78 spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
79 spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
80 *resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
81 }
82
spm_is_valid_rc_syspll(unsigned int cpu,int state_id)83 bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
84 {
85 (void)cpu;
86 (void)state_id;
87
88 return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
89 }
90
spm_update_rc_syspll(int state_id,int type,const void * val)91 int spm_update_rc_syspll(int state_id, int type, const void *val)
92 {
93 const struct mt_spm_cond_tables *tlb;
94 const struct mt_spm_cond_tables *tlb_check;
95 int res = MT_RM_STATUS_OK;
96
97 if (val == NULL) {
98 return MT_RM_STATUS_BAD;
99 }
100
101 if (type == PLAT_RC_UPDATE_CONDITION) {
102 tlb = (const struct mt_spm_cond_tables *)val;
103 tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
104
105 status.cond_block =
106 mt_spm_cond_check(state_id, tlb, tlb_check,
107 ((status.valid &
108 MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
109 &cond_syspll_res : NULL);
110 } else {
111 res = MT_RM_STATUS_BAD;
112 }
113
114 return res;
115 }
116
spm_allow_rc_syspll(int state_id)117 unsigned int spm_allow_rc_syspll(int state_id)
118 {
119 (void)state_id;
120
121 return CONSTRAINT_SYSPLL_ALLOW;
122 }
123
spm_run_rc_syspll(unsigned int cpu,int state_id)124 int spm_run_rc_syspll(unsigned int cpu, int state_id)
125 {
126 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
127 unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
128
129 (void)cpu;
130
131 if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
132 #ifdef MT_SPM_USING_SRCLKEN_RC
133 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
134 #else
135 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
136 #endif
137 }
138
139 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
140 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
141 (IS_PLAT_SUSPEND_ID(state_id) ?
142 MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
143 #else
144 (void)allows;
145 #endif
146
147 if (IS_PLAT_SUSPEND_ID(state_id)) {
148 mt_spm_suspend_enter(state_id,
149 (MT_SPM_EX_OP_SET_WDT |
150 MT_SPM_EX_OP_HW_S1_DETECT |
151 MT_SPM_EX_OP_SET_SUSPEND_MODE),
152 CONSTRAINT_SYSPLL_RESOURCE_REQ);
153 } else {
154 mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
155 }
156
157 return 0;
158 }
159
spm_reset_rc_syspll(unsigned int cpu,int state_id)160 int spm_reset_rc_syspll(unsigned int cpu, int state_id)
161 {
162 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
163 unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
164
165 (void)cpu;
166
167 if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
168 #ifdef MT_SPM_USING_SRCLKEN_RC
169 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
170 #else
171 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
172 #endif
173 }
174
175 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
176 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
177 #else
178 (void)allows;
179 #endif
180 if (IS_PLAT_SUSPEND_ID(state_id)) {
181 mt_spm_suspend_resume(state_id,
182 (MT_SPM_EX_OP_SET_SUSPEND_MODE |
183 MT_SPM_EX_OP_SET_WDT |
184 MT_SPM_EX_OP_HW_S1_DETECT),
185 NULL);
186 } else {
187 mt_spm_idle_generic_resume(state_id, ext_op, NULL);
188 status.enter_cnt++;
189 }
190
191 return 0;
192 }
193