1 /*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8
9 #include <mt_lp_rm.h>
10 #include <mt_spm.h>
11 #include <mt_spm_cond.h>
12 #include <mt_spm_constraint.h>
13 #include <mt_spm_conservation.h>
14 #include <mt_spm_idle.h>
15 #include <mt_spm_internal.h>
16 #include <mt_spm_notifier.h>
17 #include <mt_spm_rc_internal.h>
18 #include <mt_spm_reg.h>
19 #include <mt_spm_resource_req.h>
20 #include <mt_spm_suspend.h>
21 #include <plat_pm.h>
22 #include <plat_mtk_lpm.h>
23
24 #define CONSTRAINT_SYSPLL_ALLOW \
25 (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
26 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
27 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
28 MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
29
30 #define CONSTRAINT_SYSPLL_PCM_FLAG \
31 (SPM_FLAG_DISABLE_INFRA_PDN | \
32 SPM_FLAG_DISABLE_VCORE_DVS | \
33 SPM_FLAG_DISABLE_VCORE_DFS | \
34 SPM_FLAG_SRAM_SLEEP_CTRL | \
35 SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
36 SPM_FLAG_ENABLE_6315_CTRL | \
37 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |\
38 SPM_FLAG_USE_SRCCLKENO2)
39
40 #define CONSTRAINT_SYSPLL_PCM_FLAG1 0U
41 #define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
42
43 static struct mt_spm_cond_tables cond_syspll = {
44 .name = "syspll",
45 .table_cg = {
46 0xFFFFD008, /* MTCMOS1 */
47 0x20844802, /* INFRA0 */
48 0x27AF8000, /* INFRA1 */
49 0x86040640, /* INFRA2 */
50 0x30038020, /* INFRA3 */
51 0x80000000, /* INFRA4 */
52 0x00080A8B, /* PERI0 */
53 0x00004000, /* VPPSYS0_0 */
54 0x08803000, /* VPPSYS0_1 */
55 0x00000000, /* VPPSYS0_2 */
56 0x80005555, /* VPPSYS1_0 */
57 0x00009008, /* VPPSYS1_1 */
58 0x60060000, /* VDOSYS0_0 */
59 0x00000000, /* VDOSYS0_1 */
60 0x201E01F8, /* VDOSYS1_0 */
61 0x00800000, /* VDOSYS1_1 */
62 0x00000000, /* VDOSYS1_2 */
63 0x00000080, /* I2C */
64 },
65 .table_pll = 0U,
66 };
67
68 static struct mt_spm_cond_tables cond_syspll_res = {
69 .table_cg = { 0U },
70 .table_pll = 0U,
71 };
72
73 static struct constraint_status status = {
74 .id = MT_RM_CONSTRAINT_ID_SYSPLL,
75 .valid = (MT_SPM_RC_VALID_SW |
76 MT_SPM_RC_VALID_COND_LATCH |
77 MT_SPM_RC_VALID_XSOC_BBLPM),
78 .cond_block = 0U,
79 .enter_cnt = 0U,
80 .cond_res = &cond_syspll_res,
81 };
82
spm_syspll_conduct(struct spm_lp_scen * spm_lp,unsigned int * resource_req)83 static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
84 unsigned int *resource_req)
85 {
86 spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
87 spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
88 *resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
89 }
90
spm_is_valid_rc_syspll(unsigned int cpu,int state_id)91 bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
92 {
93 (void)cpu;
94 (void)state_id;
95
96 return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
97 }
98
spm_update_rc_syspll(int state_id,int type,const void * val)99 int spm_update_rc_syspll(int state_id, int type, const void *val)
100 {
101 const struct mt_spm_cond_tables *tlb;
102 const struct mt_spm_cond_tables *tlb_check;
103 int res = MT_RM_STATUS_OK;
104
105 if (val == NULL) {
106 return MT_RM_STATUS_BAD;
107 }
108
109 if (type == PLAT_RC_UPDATE_CONDITION) {
110 tlb = (const struct mt_spm_cond_tables *)val;
111 tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
112
113 status.cond_block =
114 mt_spm_cond_check(state_id, tlb, tlb_check,
115 ((status.valid &
116 MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
117 &cond_syspll_res : NULL);
118 } else {
119 res = MT_RM_STATUS_BAD;
120 }
121
122 return res;
123 }
124
spm_allow_rc_syspll(int state_id)125 unsigned int spm_allow_rc_syspll(int state_id)
126 {
127 (void)state_id;
128
129 return CONSTRAINT_SYSPLL_ALLOW;
130 }
131
spm_run_rc_syspll(unsigned int cpu,int state_id)132 int spm_run_rc_syspll(unsigned int cpu, int state_id)
133 {
134 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
135 unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
136
137 (void)cpu;
138
139 if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
140 #ifdef MT_SPM_USING_SRCLKEN_RC
141 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
142 #else
143 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
144 #endif
145 }
146
147 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
148 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
149 (IS_PLAT_SUSPEND_ID(state_id) ?
150 MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
151 #else
152 (void)allows;
153 #endif
154
155 if (IS_PLAT_SUSPEND_ID(state_id)) {
156 mt_spm_suspend_enter(state_id,
157 (MT_SPM_EX_OP_SET_WDT |
158 MT_SPM_EX_OP_HW_S1_DETECT |
159 MT_SPM_EX_OP_SET_SUSPEND_MODE),
160 CONSTRAINT_SYSPLL_RESOURCE_REQ);
161 } else {
162 mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
163 }
164
165 return 0;
166 }
167
spm_reset_rc_syspll(unsigned int cpu,int state_id)168 int spm_reset_rc_syspll(unsigned int cpu, int state_id)
169 {
170 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
171 unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
172
173 (void)cpu;
174
175 if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
176 #ifdef MT_SPM_USING_SRCLKEN_RC
177 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
178 #else
179 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
180 #endif
181 }
182
183 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
184 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
185 #else
186 (void)allows;
187 #endif
188 if (IS_PLAT_SUSPEND_ID(state_id)) {
189 mt_spm_suspend_resume(state_id,
190 (MT_SPM_EX_OP_SET_SUSPEND_MODE |
191 MT_SPM_EX_OP_SET_WDT |
192 MT_SPM_EX_OP_HW_S1_DETECT),
193 NULL);
194 } else {
195 mt_spm_idle_generic_resume(state_id, ext_op, NULL);
196 status.enter_cnt++;
197 }
198
199 return 0;
200 }
201